File: proxy-reg-erasure.mir

package info (click to toggle)
llvm-toolchain-20 1%3A20.1.8-1~exp1
  • links: PTS, VCS
  • area: main
  • in suites: experimental
  • size: 2,111,388 kB
  • sloc: cpp: 7,438,767; ansic: 1,393,871; asm: 1,012,926; python: 241,728; f90: 86,635; objc: 75,411; lisp: 42,144; pascal: 17,286; sh: 10,027; ml: 5,082; perl: 4,730; awk: 3,523; makefile: 3,349; javascript: 2,251; xml: 892; fortran: 672
file content (98 lines) | stat: -rw-r--r-- 3,061 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
# RUN: llc %s --run-pass=nvptx-proxyreg-erasure -mtriple=nvptx64 -o - | FileCheck %s

--- |
  ; ModuleID = 'third-party/llvm-project/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll'
  source_filename = "third-party/llvm-project/llvm/test/CodeGen/NVPTX/proxy-reg-erasure-mir.ll"
  target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"

  declare <4 x i32> @callee_vec_i32()

  define <4 x i32> @check_vec_i32() {
    %ret = call <4 x i32> @callee_vec_i32()
    ret <4 x i32> %ret
  }

...
---
name:            check_vec_i32
alignment:       1
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
callsEHReturn:   false
callsUnwindInit: false
hasEHCatchret:   false
hasEHScopes:     false
hasEHFunclets:   false
isOutlined:      false
debugInstrRef:   false
failsVerification: false
tracksDebugUserValues: false
registers:
  - { id: 0, class: int32regs, preferred-register: '' }
  - { id: 1, class: int32regs, preferred-register: '' }
  - { id: 2, class: int32regs, preferred-register: '' }
  - { id: 3, class: int32regs, preferred-register: '' }
  - { id: 4, class: int32regs, preferred-register: '' }
  - { id: 5, class: int32regs, preferred-register: '' }
  - { id: 6, class: int32regs, preferred-register: '' }
  - { id: 7, class: int32regs, preferred-register: '' }
  - { id: 8, class: int32regs, preferred-register: '' }
  - { id: 9, class: int32regs, preferred-register: '' }
  - { id: 10, class: int32regs, preferred-register: '' }
  - { id: 11, class: int32regs, preferred-register: '' }
liveins:         []
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       0
  offsetAdjustment: 0
  maxAlignment:    1
  adjustsStack:    false
  hasCalls:        true
  stackProtector:  ''
  functionContext: ''
  maxCallFrameSize: 4294967295
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  hasTailCall:     false
  isCalleeSavedInfoValid: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:           []
entry_values:    []
callSites:       []
debugValueSubstitutions: []
constants:       []
machineFunctionInfo: {}
body:             |
  bb.0:
    %0:int32regs, %1:int32regs, %2:int32regs, %3:int32regs = LoadParamMemV4I32 0
    ; CHECK-NOT: ProxyReg
    %4:int32regs = ProxyRegI32 killed %0
    %5:int32regs = ProxyRegI32 killed %1
    %6:int32regs = ProxyRegI32 killed %2
    %7:int32regs = ProxyRegI32 killed %3
    ; CHECK: StoreRetvalV4I32 killed %0, killed %1, killed %2, killed %3
    StoreRetvalV4I32 killed %4, killed %5, killed %6, killed %7, 0

    %8:int32regs = LoadParamMemI32 0
    ; CHECK-NOT: ProxyReg
    %9:int32regs = ProxyRegI32 killed %8
    %10:int32regs = ProxyRegI32 killed %9
    %11:int32regs = ProxyRegI32 killed %10
    ; CHECK: StoreRetvalI32 killed %8
    StoreRetvalI32 killed %11, 0
    Return

...