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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
define float @call_ldexpf(float %a, i32 %b) {
; CHECK-LABEL: call_ldexpf:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: bl ldexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call float @ldexpf(float %a, i32 %b)
ret float %result
}
define double @call_ldexp(double %a, i32 %b) {
; CHECK-LABEL: call_ldexp:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: bl ldexp
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call double @ldexp(double %a, i32 %b)
ret double %result
}
define ppc_fp128 @call_ldexpl(ppc_fp128 %a, i32 %b) {
; CHECK-LABEL: call_ldexpl:
; CHECK: # %bb.0:
; CHECK-NEXT: mflr r0
; CHECK-NEXT: stdu r1, -32(r1)
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: clrldi r5, r5, 32
; CHECK-NEXT: bl ldexpl
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
%result = call ppc_fp128 @ldexpl(ppc_fp128 %a, i32 %b)
ret ppc_fp128 %result
}
declare float @ldexpf(float %a, i32 %b) #0
declare double @ldexp(double %a, i32 %b) #0
declare ppc_fp128 @ldexpl(ppc_fp128 %a, i32 %b) #0
attributes #0 = { nounwind readonly }
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