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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=ppc64le-unknown-unknown %s -o - | FileCheck %s
define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-LABEL: scmp_8_8:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
ret i8 %1
}
define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-LABEL: scmp_8_16:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 5, 4, 3
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: rldicl 5, 5, 1, 63
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
ret i8 %1
}
define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scmp_8_32:
; CHECK: # %bb.0:
; CHECK-NEXT: extsw 4, 4
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
ret i8 %1
}
define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: scmp_8_64:
; CHECK: # %bb.0:
; CHECK-NEXT: sradi 5, 4, 63
; CHECK-NEXT: rldicl 6, 3, 1, 63
; CHECK-NEXT: subc 7, 4, 3
; CHECK-NEXT: adde 5, 6, 5
; CHECK-NEXT: cmpd 3, 4
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
ret i8 %1
}
define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
; CHECK-LABEL: scmp_8_128:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpld 4, 6
; CHECK-NEXT: cmpd 1, 4, 6
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: cmpld 5, 3, 5
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: crandc 22, 5, 2
; CHECK-NEXT: crand 21, 2, 21
; CHECK-NEXT: crand 20, 2, 20
; CHECK-NEXT: crnor 21, 21, 22
; CHECK-NEXT: isel 3, 0, 3, 21
; CHECK-NEXT: crandc 21, 4, 2
; CHECK-NEXT: cror 20, 20, 21
; CHECK-NEXT: isel 3, 4, 3, 20
; CHECK-NEXT: blr
%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
ret i8 %1
}
define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {
; CHECK-LABEL: scmp_32_32:
; CHECK: # %bb.0:
; CHECK-NEXT: extsw 4, 4
; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: cmpw 3, 4
; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: li 4, -1
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: isellt 3, 4, 3
; CHECK-NEXT: blr
%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
ret i32 %1
}
define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: scmp_32_64:
; CHECK: # %bb.0:
; CHECK-NEXT: sradi 5, 4, 63
; CHECK-NEXT: rldicl 6, 3, 1, 63
; CHECK-NEXT: subc 7, 4, 3
; CHECK-NEXT: adde 5, 6, 5
; CHECK-NEXT: cmpd 3, 4
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
ret i32 %1
}
define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: scmp_64_64:
; CHECK: # %bb.0:
; CHECK-NEXT: sradi 5, 4, 63
; CHECK-NEXT: rldicl 6, 3, 1, 63
; CHECK-NEXT: subc 7, 4, 3
; CHECK-NEXT: adde 5, 6, 5
; CHECK-NEXT: cmpd 3, 4
; CHECK-NEXT: li 3, -1
; CHECK-NEXT: xori 5, 5, 1
; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: blr
%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
ret i64 %1
}
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