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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV32I-MO %s
# RUN: llc -mtriple=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefixes=RV64I-MO %s
# MIR has been edited by hand to have x5 as live out in @dont_outline
---
name: outline_0
tracksRegLiveness: true
isOutlined: false
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_0
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET implicit $x11
;
; RV64I-MO-LABEL: name: outline_0
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET implicit $x11
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x11
...
---
name: dont_outline
tracksRegLiveness: true
isOutlined: false
body: |
; RV32I-MO-LABEL: name: dont_outline
; RV32I-MO: bb.0:
; RV32I-MO-NEXT: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x11 = ORI $x11, 1023
; RV32I-MO-NEXT: $x12 = ADDI $x10, 17
; RV32I-MO-NEXT: $x11 = AND $x12, $x11
; RV32I-MO-NEXT: $x10 = SUB $x10, $x11
; RV32I-MO-NEXT: BEQ $x10, $x11, %bb.1
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: bb.1:
; RV32I-MO-NEXT: liveins: $x10, $x5
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: PseudoRET implicit $x10, implicit $x5
;
; RV64I-MO-LABEL: name: dont_outline
; RV64I-MO: bb.0:
; RV64I-MO-NEXT: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x11 = ORI $x11, 1023
; RV64I-MO-NEXT: $x12 = ADDI $x10, 17
; RV64I-MO-NEXT: $x11 = AND $x12, $x11
; RV64I-MO-NEXT: $x10 = SUB $x10, $x11
; RV64I-MO-NEXT: BEQ $x10, $x11, %bb.1
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: bb.1:
; RV64I-MO-NEXT: liveins: $x10, $x5
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: PseudoRET implicit $x10, implicit $x5
bb.0:
liveins: $x10, $x11
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
BEQ $x10, $x11, %bb.1
bb.1:
liveins: $x10, $x5
PseudoRET implicit $x10, implicit $x5
...
---
name: outline_1
tracksRegLiveness: true
isOutlined: false
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_1
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET implicit $x10
;
; RV64I-MO-LABEL: name: outline_1
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET implicit $x10
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: outline_2
tracksRegLiveness: true
isOutlined: false
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_2
; RV32I-MO: liveins: $x10, $x11
; RV32I-MO-NEXT: {{ $}}
; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV32I-MO-NEXT: PseudoRET implicit $x12
;
; RV64I-MO-LABEL: name: outline_2
; RV64I-MO: liveins: $x10, $x11
; RV64I-MO-NEXT: {{ $}}
; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
; RV64I-MO-NEXT: PseudoRET implicit $x12
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x12
...
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