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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S -data-layout="E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" | FileCheck %s
define void @PR35618(ptr %st1, ptr %st2) {
; CHECK-LABEL: @PR35618(
; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8
; CHECK-NEXT: [[TMP:%.*]] = fcmp olt double [[LD1]], [[LD2]]
; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP]], double [[LD1]], double [[LD2]]
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
; CHECK-NEXT: ret void
;
%y1 = alloca double
%z1 = alloca double
%ld1 = load double, ptr %y1
%ld2 = load double, ptr %z1
%tmp = fcmp olt double %ld1, %ld2
%sel = select i1 %tmp, ptr %y1, ptr %z1
%tmp12 = load i64, ptr %sel
store i64 %tmp12, ptr %st1
store i64 %tmp12, ptr %st2
ret void
}
define void @PR35618_asan(ptr %st1, ptr %st2) sanitize_address {
; CHECK-LABEL: @PR35618_asan(
; CHECK-NEXT: [[Y1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[Z1:%.*]] = alloca double, align 8
; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1]], align 8
; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1]], align 8
; CHECK-NEXT: [[TMP:%.*]] = fcmp olt double [[LD1]], [[LD2]]
; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP]], double [[LD1]], double [[LD2]]
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
; CHECK-NEXT: ret void
;
%y1 = alloca double
%z1 = alloca double
%ld1 = load double, ptr %y1
%ld2 = load double, ptr %z1
%tmp = fcmp olt double %ld1, %ld2
%sel = select i1 %tmp, ptr %y1, ptr %z1
%tmp12 = load i64, ptr %sel
store i64 %tmp12, ptr %st1
store i64 %tmp12, ptr %st2
ret void
}
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