1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
define i32 @rocrand_regression(ptr addrspace(1) %arg, i32 %arg0, i1 %cmp7) {
; CHECK-LABEL: rocrand_regression:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v3
; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, v0
; CHECK-NEXT: s_mov_b32 s8, 0
; CHECK-NEXT: .LBB0_1: ; %do.body
; CHECK-NEXT: ; =>This Loop Header: Depth=1
; CHECK-NEXT: ; Child Loop BB0_2 Depth 2
; CHECK-NEXT: s_mov_b64 s[6:7], 0
; CHECK-NEXT: .LBB0_2: ; %while.cond
; CHECK-NEXT: ; Parent Loop BB0_1 Depth=1
; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
; CHECK-NEXT: s_and_b64 s[10:11], exec, s[4:5]
; CHECK-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
; CHECK-NEXT: s_andn2_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_cbranch_execnz .LBB0_2
; CHECK-NEXT: ; %bb.3: ; %do.cond
; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
; CHECK-NEXT: s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT: s_or_b32 s8, s8, 1
; CHECK-NEXT: s_cbranch_execnz .LBB0_1
; CHECK-NEXT: ; %bb.4: ; %DummyReturnBlock
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
br label %do.body
do.body: ; preds = %do.cond, %entry
%phi.0 = phi i32 [ %arg0, %do.cond ], [ 0, %entry ]
%phi.1 = phi i32 [ %add6, %do.cond ], [ 0, %entry ]
%add6 = or i32 %phi.1, 1
store i32 %phi.1, ptr addrspace(1) %arg, align 4
br label %while.cond
while.cond: ; preds = %while.cond, %do.body
%phi.2 = phi i32 [ %phi.0, %do.body ], [ 0, %while.cond ]
br i1 %cmp7, label %while.cond, label %do.cond
do.cond: ; preds = %while.cond
br i1 true, label %do.body, label %do.end
do.end: ; preds = %do.cond
ret i32 %phi.2
}
|
