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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -o - %s | FileCheck %s
---
name: issue130646
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: issue130646
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr10
; CHECK-NEXT: S_BRANCH %bb.3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI %13, %bb.3, %5, %bb.4
; CHECK-NEXT: S_CMP_LG_U32 1, 1, implicit-def $scc
; CHECK-NEXT: S_CBRANCH_SCC1 %bb.3, implicit $scc
; CHECK-NEXT: S_BRANCH %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: $vgpr0 = COPY [[COPY]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.4(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[COPY1]], %bb.0, [[PHI]], %bb.1
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0
; CHECK-NEXT: S_CMP_EQ_U64 [[PHI1]], killed [[S_MOV_B64_]], implicit-def $scc
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub0
; CHECK-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY2]].sub1
; CHECK-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
; CHECK-NEXT: S_CBRANCH_SCC1 %bb.1, implicit $scc
; CHECK-NEXT: S_BRANCH %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], [[COPY3]], implicit-def dead $scc
; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_LSHR_B64_]].sub1
; CHECK-NEXT: [[S_LSHR_B64_1:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], killed [[COPY6]], implicit-def dead $scc
; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[S_LSHR_B64_1]].sub1
; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 killed [[COPY7]], [[COPY3]], implicit-def dead $scc
; CHECK-NEXT: [[S_LSHR_B64_2:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[PHI1]], killed [[S_OR_B32_]], implicit-def dead $scc
; CHECK-NEXT: S_BRANCH %bb.1
bb.0:
liveins: $vgpr0, $vgpr1_vgpr2, $sgpr8_sgpr9, $sgpr10
%0:vgpr_32 = COPY $vgpr0
%1:sreg_64 = COPY $sgpr8_sgpr9
%2:vreg_64 = COPY $vgpr1_vgpr2
%3:sreg_32 = COPY $sgpr10
S_BRANCH %bb.3
bb.1:
%4:sreg_64 = PHI %2, %bb.3, %5, %bb.4
S_CMP_LG_U32 1, 1, implicit-def $scc
S_CBRANCH_SCC1 %bb.3, implicit $scc
S_BRANCH %bb.2
bb.2:
$vgpr0 = COPY %0
SI_RETURN implicit $vgpr0
bb.3:
%6:sreg_64 = PHI %1, %bb.0, %4, %bb.1
%7:sreg_64 = S_MOV_B64 0
S_CMP_EQ_U64 %6, killed %7, implicit-def $scc
S_CBRANCH_SCC1 %bb.1, implicit $scc
S_BRANCH %bb.4
bb.4:
%8:sreg_64 = S_LSHR_B64 %6, %3, implicit-def dead $scc
%9:sreg_32 = COPY %8.sub1
%10:sreg_64 = S_LSHR_B64 %6, killed %9, implicit-def dead $scc
%11:sreg_32 = COPY %10.sub1
%12:sreg_32 = S_OR_B32 killed %11, %3, implicit-def dead $scc
%5:sreg_64 = S_LSHR_B64 %6, killed %12, implicit-def dead $scc
S_BRANCH %bb.1
...
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