1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
;RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define amdgpu_ps void @test(<4 x float> inreg %reg0) {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = extractelement <4 x float> %reg0, i32 1
%r2 = extractelement <4 x float> %reg0, i32 2
%r3 = fmul float %r0, %r1
%r4 = fadd float %r3, %r2
%vec = insertelement <4 x float> poison, float %r4, i32 0
call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
ret void
}
declare float @fabs(float ) readnone
declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
|
