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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx90a %s -o - | FileCheck %s
define amdgpu_ps float @kill_true(i1 %.not) {
; CHECK-LABEL: kill_true:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_mov_b64 s[0:1], exec
; CHECK-NEXT: s_wqm_b64 exec, exec
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 1, v0
; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc
; CHECK-NEXT: s_cbranch_execz .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %if1
; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: ; kill: def $sgpr4 killed $sgpr4 killed $exec
; CHECK-NEXT: v_pk_mov_b32 v[0:1], 0, 0
; CHECK-NEXT: v_mov_b32_e32 v2, s4
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: .LBB0_2: ; %endif1
; CHECK-NEXT: s_or_b64 exec, exec, s[2:3]
; CHECK-NEXT: s_and_b64 exec, exec, s[0:1]
; CHECK-NEXT: v_mov_b32_e32 v0, 0
; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT: ; return to shader part epilog
entry:
br i1 %.not, label %endif1, label %if1
if1:
%C = call float @llvm.amdgcn.wqm.f32(float 0.000000e+00)
store float %C, ptr null, align 4
br label %endif1
endif1:
call void @llvm.amdgcn.kill(i1 true)
ret float 0.000000e+00
}
declare void @llvm.amdgcn.kill(i1)
declare float @llvm.amdgcn.wqm.f32(float)
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