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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250 %s
declare float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32, i32)
define float @test_cvt_f32_fp8_e5m3_byte0(i32 %a) {
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte0:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 clamp
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 0)
ret float %ret
}
define float @test_cvt_f32_fp8_e5m3_byte1(i32 %a) {
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:1 clamp
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 1)
ret float %ret
}
define float @test_cvt_f32_fp8_e5m3_byte2(i32 %a) {
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte2:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:2 clamp
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 2)
ret float %ret
}
define float @test_cvt_f32_fp8_e5m3_byte3(i32 %a) {
; GFX1250-LABEL: test_cvt_f32_fp8_e5m3_byte3:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: v_cvt_f32_fp8_e64 v0, v0 byte_sel:3 clamp
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
%ret = tail call float @llvm.amdgcn.cvt.f32.fp8.e5m3(i32 %a, i32 3)
ret float %ret
}
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