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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define <2 x i8> @test_v16i8_v2i32_824(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_v16i8_v2i32_824:
; CHECK: // %bb.0:
; CHECK-NEXT: mov b0, v0.b[8]
; CHECK-NEXT: mov v0.b[4], v1.b[8]
; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%c = shufflevector <16 x i8> %a, <16 x i8> %b, <2 x i32> <i32 8, i32 24>
%d = add <2 x i8> %c, %c
ret <2 x i8> %d
}
define <2 x i8> @test_v16i8_v2i32_016(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_v16i8_v2i32_016:
; CHECK: // %bb.0:
; CHECK-NEXT: mov b0, v0.b[0]
; CHECK-NEXT: mov v0.b[4], v1.b[0]
; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%c = shufflevector <16 x i8> %a, <16 x i8> %b, <2 x i32> <i32 0, i32 16>
%d = add <2 x i8> %c, %c
ret <2 x i8> %d
}
define <2 x i8> @test_v8i8_v2i32_08(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: test_v8i8_v2i32_08:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov b0, v0.b[0]
; CHECK-NEXT: mov v0.b[4], v1.b[0]
; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%c = shufflevector <8 x i8> %a, <8 x i8> %b, <2 x i32> <i32 0, i32 8>
%d = add <2 x i8> %c, %c
ret <2 x i8> %d
}
define <2 x i16> @test_v8i16_v2i32_08(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_v8i16_v2i32_08:
; CHECK: // %bb.0:
; CHECK-NEXT: mov h0, v0.h[0]
; CHECK-NEXT: mov v0.h[2], v1.h[0]
; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%c = shufflevector <8 x i16> %a, <8 x i16> %b, <2 x i32> <i32 0, i32 8>
%d = add <2 x i16> %c, %c
ret <2 x i16> %d
}
define <2 x i16> @test_v4i16_v2i32_04(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: test_v4i16_v2i32_04:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov h0, v0.h[0]
; CHECK-NEXT: mov v0.h[2], v1.h[0]
; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
; CHECK-NEXT: ret
%c = shufflevector <4 x i16> %a, <4 x i16> %b, <2 x i32> <i32 0, i32 4>
%d = add <2 x i16> %c, %c
ret <2 x i16> %d
}
define <4 x i8> @test_v16i8_v4i16_824(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_v16i8_v4i16_824:
; CHECK: // %bb.0:
; CHECK-NEXT: mov b2, v0.b[8]
; CHECK-NEXT: mov v2.b[2], v1.b[8]
; CHECK-NEXT: mov v2.b[4], v0.b[0]
; CHECK-NEXT: mov v2.b[6], v1.b[0]
; CHECK-NEXT: add v0.4h, v2.4h, v2.4h
; CHECK-NEXT: ret
%c = shufflevector <16 x i8> %a, <16 x i8> %b, <4 x i32> <i32 8, i32 24, i32 0, i32 16>
%d = add <4 x i8> %c, %c
ret <4 x i8> %d
}
define <4 x i8> @test_v16i8_v4i16_016(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_v16i8_v4i16_016:
; CHECK: // %bb.0:
; CHECK-NEXT: mov b2, v0.b[0]
; CHECK-NEXT: mov v2.b[2], v1.b[0]
; CHECK-NEXT: mov v2.b[4], v0.b[4]
; CHECK-NEXT: mov v2.b[6], v1.b[4]
; CHECK-NEXT: add v0.4h, v2.4h, v2.4h
; CHECK-NEXT: ret
%c = shufflevector <16 x i8> %a, <16 x i8> %b, <4 x i32> <i32 0, i32 16, i32 4, i32 20>
%d = add <4 x i8> %c, %c
ret <4 x i8> %d
}
define <4 x i8> @test_v8i8_v4i16_08(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: test_v8i8_v4i16_08:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT: mov b2, v0.b[0]
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-NEXT: mov v2.b[2], v1.b[0]
; CHECK-NEXT: mov v2.b[4], v0.b[4]
; CHECK-NEXT: mov v2.b[6], v1.b[4]
; CHECK-NEXT: add v0.4h, v2.4h, v2.4h
; CHECK-NEXT: ret
%c = shufflevector <8 x i8> %a, <8 x i8> %b, <4 x i32> <i32 0, i32 8, i32 4, i32 12>
%d = add <4 x i8> %c, %c
ret <4 x i8> %d
}
define <4 x i16> @test_v8i16_v4i16_08(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: test_v8i16_v4i16_08:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI8_0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
; CHECK-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%c = shufflevector <8 x i16> %a, <8 x i16> %b, <4 x i32> <i32 0, i32 7, i32 6, i32 12>
%d = add <4 x i16> %c, %c
ret <4 x i16> %d
}
define <4 x i16> @test_v4i16_v4i16_04(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: test_v4i16_v4i16_04:
; CHECK: // %bb.0:
; CHECK-NEXT: ext v1.8b, v1.8b, v0.8b, #2
; CHECK-NEXT: trn2 v0.4h, v1.4h, v0.4h
; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4
; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
; CHECK-NEXT: ret
%c = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 3, i32 5, i32 6>
%d = add <4 x i16> %c, %c
ret <4 x i16> %d
}
define i1 @test1(ptr %add.ptr, ptr %result, <2 x i64> %hi, <2 x i64> %lo) {
; CHECK-LABEL: test1:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: movi v3.16b, #1
; CHECK-NEXT: mov w12, #1 // =0x1
; CHECK-NEXT: cmgt v0.2d, v2.2d, v0.2d
; CHECK-NEXT: cmgt v4.2d, v1.2d, v2.2d
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
; CHECK-NEXT: umov w8, v0.b[8]
; CHECK-NEXT: umov w9, v3.b[8]
; CHECK-NEXT: umov w10, v0.b[0]
; CHECK-NEXT: umov w11, v3.b[0]
; CHECK-NEXT: sub v0.2d, v2.2d, v1.2d
; CHECK-NEXT: dup v1.2d, x12
; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: add v0.2d, v0.2d, v1.2d
; CHECK-NEXT: orr w8, w10, w8, lsl #1
; CHECK-NEXT: orr w8, w8, w11
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: tst w8, #0x3
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%19 = load <2 x i64>, ptr %add.ptr, align 8
%cmp = icmp sgt <2 x i64> %19, %hi
%sext = sext <2 x i1> %cmp to <2 x i64>
%20 = bitcast <2 x i64> %sext to <16 x i8>
%21 = and <16 x i8> %20, <i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>
%storedv = extractelement <16 x i8> %21, i64 0
%storedv.1 = extractelement <16 x i8> %21, i64 8
%22 = shl nuw nsw i8 %storedv.1, 1
%or.111 = or disjoint i8 %22, %storedv
%cmp101 = icmp slt <2 x i64> %19, %lo
%sext102 = sext <2 x i1> %cmp101 to <2 x i64>
%23 = bitcast <2 x i64> %sext102 to <16 x i8>
%24 = and <16 x i8> %23, <i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>
%storedv104 = extractelement <16 x i8> %24, i64 0
%storedv.1105 = extractelement <16 x i8> %24, i64 8
%25 = shl nuw nsw i8 %storedv.1105, 1
%or.111106 = or disjoint i8 %25, %storedv104
%reass.sub = sub <2 x i64> %19, %lo
%add = add <2 x i64> %reass.sub, splat (i64 1)
store <2 x i64> %add, ptr %result, align 8
%or118 = or i8 %or.111, %or.111106
%cmp24.not = icmp eq i8 %or118, 0
ret i1 %cmp24.not
}
define i1 @test2(ptr %add.ptr, ptr %result, <2 x i64> %hi, <2 x i64> %lo) {
; CHECK-LABEL: test2:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q2, [x0]
; CHECK-NEXT: movi v3.16b, #1
; CHECK-NEXT: mov w9, #1 // =0x1
; CHECK-NEXT: cmgt v0.2d, v2.2d, v0.2d
; CHECK-NEXT: cmgt v4.2d, v1.2d, v2.2d
; CHECK-NEXT: sub v1.2d, v2.2d, v1.2d
; CHECK-NEXT: dup v2.2d, x9
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
; CHECK-NEXT: and v3.16b, v4.16b, v3.16b
; CHECK-NEXT: mov b5, v0.b[8]
; CHECK-NEXT: mov b0, v0.b[0]
; CHECK-NEXT: mov v5.b[4], v3.b[8]
; CHECK-NEXT: mov v0.b[4], v3.b[0]
; CHECK-NEXT: add v3.2s, v5.2s, v5.2s
; CHECK-NEXT: orr v0.8b, v3.8b, v0.8b
; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: add v0.2d, v1.2d, v2.2d
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: orr w8, w9, w8
; CHECK-NEXT: tst w8, #0xff
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
%1 = load <2 x i64>, ptr %add.ptr, align 8
%cmp = icmp sgt <2 x i64> %1, %hi
%sext = sext <2 x i1> %cmp to <2 x i64>
%2 = bitcast <2 x i64> %sext to <16 x i8>
%3 = and <16 x i8> %2, <i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>
%cmp101 = icmp slt <2 x i64> %1, %lo
%sext102 = sext <2 x i1> %cmp101 to <2 x i64>
%4 = bitcast <2 x i64> %sext102 to <16 x i8>
%5 = and <16 x i8> %4, <i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 1, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>
%6 = shufflevector <16 x i8> %3, <16 x i8> %5, <2 x i32> <i32 8, i32 24>
%7 = shl nuw nsw <2 x i8> %6, splat (i8 1)
%8 = shufflevector <16 x i8> %3, <16 x i8> %5, <2 x i32> <i32 0, i32 16>
%9 = or disjoint <2 x i8> %7, %8
%reass.sub = sub <2 x i64> %1, %lo
%add = add <2 x i64> %reass.sub, splat (i64 1)
store <2 x i64> %add, ptr %result, align 8
%10 = extractelement <2 x i8> %9, i32 0
%11 = extractelement <2 x i8> %9, i32 1
%or118 = or i8 %10, %11
%cmp24.not = icmp eq i8 %or118, 0
ret i1 %cmp24.not
}
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