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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
define void @fptrunc2_f64_f32(ptr %dst, ptr %src) {
; CHECK-LABEL: fptrunc2_f64_f32:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr z0, [x1]
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
; CHECK-NEXT: st1w { z0.d }, p0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <vscale x 2 x double>, ptr %src, align 8
%1 = fptrunc <vscale x 2 x double> %0 to <vscale x 2 x float>
store <vscale x 2 x float> %1, ptr %dst, align 4
ret void
}
define void @fptrunc2_f64_f16(ptr %dst, ptr %src) {
; CHECK-LABEL: fptrunc2_f64_f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr z0, [x1]
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
; CHECK-NEXT: st1h { z0.d }, p0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <vscale x 2 x double>, ptr %src, align 8
%1 = fptrunc <vscale x 2 x double> %0 to <vscale x 2 x half>
store <vscale x 2 x half> %1, ptr %dst, align 2
ret void
}
define void @fptrunc4_f32_f16(ptr %dst, ptr %src) {
; CHECK-LABEL: fptrunc4_f32_f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr z0, [x1]
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
; CHECK-NEXT: st1h { z0.s }, p0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <vscale x 4 x float>, ptr %src, align 8
%1 = fptrunc <vscale x 4 x float> %0 to <vscale x 4 x half>
store <vscale x 4 x half> %1, ptr %dst, align 2
ret void
}
define void @fptrunc2_f32_f16(ptr %dst, ptr %src) {
; CHECK-LABEL: fptrunc2_f32_f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x1]
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
; CHECK-NEXT: st1h { z0.d }, p0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <vscale x 2 x float>, ptr %src, align 8
%1 = fptrunc <vscale x 2 x float> %0 to <vscale x 2 x half>
store <vscale x 2 x half> %1, ptr %dst, align 2
ret void
}
define void @fptrunc8_f64_f16(ptr %dst, ptr %src) {
; CHECK-LABEL: fptrunc8_f64_f16:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr z0, [x1, #3, mul vl]
; CHECK-NEXT: ldr z1, [x1]
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ldr z2, [x1, #1, mul vl]
; CHECK-NEXT: ldr z3, [x1, #2, mul vl]
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
; CHECK-NEXT: fcvt z1.h, p0/m, z1.d
; CHECK-NEXT: fcvt z3.h, p0/m, z3.d
; CHECK-NEXT: fcvt z2.h, p0/m, z2.d
; CHECK-NEXT: uzp1 z0.s, z3.s, z0.s
; CHECK-NEXT: uzp1 z1.s, z1.s, z2.s
; CHECK-NEXT: uzp1 z0.h, z1.h, z0.h
; CHECK-NEXT: str z0, [x0]
; CHECK-NEXT: ret
entry:
%0 = load <vscale x 8 x double>, ptr %src, align 8
%1 = fptrunc <vscale x 8 x double> %0 to <vscale x 8 x half>
store <vscale x 8 x half> %1, ptr %dst, align 2
ret void
}
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