1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
# RUN: not --crash llc -mtriple=aarch64 -run-pass machineverifier -o /dev/null %s 2>&1 | FileCheck -implicit-check-not="Bad machine code" %s
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRSui $s1, $x0, 4096
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRSui $s1, $x0, -1
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0, $w1 = LDRWpre $x0(tied-def 0), 256
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0, $w1 = LDRWpre $x0(tied-def 0), -257
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0, $w1 = LDRWpre $x0(tied-def 0), 256
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0, $w1 = LDRWpre $x0(tied-def 0), -257
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRBBui $w1, $x0, 4096
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRBBui $w1, $x0, -1
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRHHui $w1, $x0, 4096
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: STRHHui $w1, $x0, -1
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0 = STRSpost $s1, $x0(tied-def 0), 256
# CHECK: *** Bad machine code: Unexpected immediate on load/store instruction ***
# CHECK: - instruction: early-clobber $x0 = STRSpost $s1, $x0(tied-def 0), -257
---
name: testoffsets
alignment: 4
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $d0, $s1, $q2, $x0, $w1
STRSui $s1, $x0, 4095
STRSui $s1, $x0, 4096
STRSui $s1, $x0, 0
STRSui $s1, $x0, -1
$x0, $w1 = LDRWpre $x0, 256
$x0, $w1 = LDRWpre $x0, -257
$x0, $w1 = LDRWpre $x0, 256
$x0, $w1 = LDRWpre $x0, -257
STRBBui $w1, $x0, 4096
STRBBui $w1, $x0, -1
STRHHui $w1, $x0, 4096
STRHHui $w1, $x0, -1
$x0 = STRSpost $s1, $x0, 256
$x0 = STRSpost $s1, $x0, -257
RET undef $lr, implicit $x0
...
|
