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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck -check-prefixes=GCN,PRELEGAL %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck -check-prefixes=GCN,RBCOMB %s
---
name: trunc_sext_i32_i16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: trunc_sext_i32_i16
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 16
; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...
---
name: trunc_sext_i32_i8
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; GCN-LABEL: name: trunc_sext_i32_i8
; GCN: liveins: $vgpr0
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 8
; GCN-NEXT: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s8) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...
---
name: trunc_sext_i64_i32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: trunc_sext_i64_i32
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
; GCN-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0
%2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: trunc_sext_v4i32_v4i16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; PRELEGAL-LABEL: name: trunc_sext_v4i32_v4i16
; PRELEGAL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; PRELEGAL-NEXT: {{ $}}
; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s32>) = G_SEXT_INREG [[COPY]], 16
; PRELEGAL-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT_INREG]](<4 x s32>)
;
; RBCOMB-LABEL: name: trunc_sext_v4i32_v4i16
; RBCOMB: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; RBCOMB-NEXT: {{ $}}
; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[COPY]](<4 x s32>)
; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[TRUNC]](<4 x s16>)
; RBCOMB-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[SEXT]](<4 x s32>)
%0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<4 x s16>) = G_TRUNC %0
%2:_(<4 x s32>) = G_SEXT %1
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %2
...
---
name: trunc_sext_v4i16_v4i8
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; PRELEGAL-LABEL: name: trunc_sext_v4i16_v4i8
; PRELEGAL: liveins: $vgpr0_vgpr1
; PRELEGAL-NEXT: {{ $}}
; PRELEGAL-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; PRELEGAL-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<4 x s16>) = G_SEXT_INREG [[COPY]], 8
; PRELEGAL-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<4 x s16>)
;
; RBCOMB-LABEL: name: trunc_sext_v4i16_v4i8
; RBCOMB: liveins: $vgpr0_vgpr1
; RBCOMB-NEXT: {{ $}}
; RBCOMB-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
; RBCOMB-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s8>) = G_TRUNC [[COPY]](<4 x s16>)
; RBCOMB-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s16>) = G_SEXT [[TRUNC]](<4 x s8>)
; RBCOMB-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](<4 x s16>)
%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
%1:_(<4 x s8>) = G_TRUNC %0
%2:_(<4 x s16>) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: trunc_sext_mismatching_types
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; GCN-LABEL: name: trunc_sext_mismatching_types
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; GCN-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[TRUNC]](s16)
; GCN-NEXT: $vgpr0 = COPY [[SEXT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s16) = G_TRUNC %0
%2:_(s32) = G_SEXT %1
$vgpr0 = COPY %2
...
|
