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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
--- |
define i32 @widen_load_range0_tbaa(ptr addrspace(1) %ptr) {
%load = load i24, ptr addrspace(1) %ptr, !range !0, !tbaa !1
%zext = zext i24 %load to i32
ret i32 %zext
}
define i32 @widen_load_range1_tbaa(ptr addrspace(1) %ptr) {
%load = load i24, ptr addrspace(1) %ptr, !range !0, !tbaa !1
%zext = zext i24 %load to i32
ret i32 %zext
}
define i32 @widen_load_tbaa0(ptr addrspace(1) %ptr) {
%load = load i24, ptr addrspace(1) %ptr, !tbaa !1
%zext = zext i24 %load to i32
ret i32 %zext
}
define i32 @widen_load_tbaa1(ptr addrspace(1) %ptr) {
%load = load i24, ptr addrspace(1) %ptr, !tbaa !1
%zext = zext i24 %load to i32
ret i32 %zext
}
!0 = !{i24 0, i24 1048575}
!1 = !{!"omnipotent char", !2}
!2 = !{!"Simple C/C++ TBAA"}
!3 = !{i24 0, i24 1048575}
...
# Make sure range metadata is not preserved when widening loads, but
# tbaa is.
---
name: widen_load_range0_tbaa
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: widen_load_range0_tbaa
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !0, !tbaa !1)
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
# Result register type already matches the widened memory type.
---
name: widen_load_range1_tbaa
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: widen_load_range1_tbaa
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !range !3, !tbaa !1)
$vgpr0 = COPY %1
...
---
name: widen_load_tbaa0
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: widen_load_tbaa0
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; SI-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C]]
; SI-NEXT: $vgpr0 = COPY [[AND]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s24) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)
%2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2
...
# Result register type already matches the widened memory type.
---
name: widen_load_tbaa1
body: |
bb.0:
liveins: $vgpr0_vgpr1
; SI-LABEL: name: widen_load_tbaa1
; SI: liveins: $vgpr0_vgpr1
; SI-NEXT: {{ $}}
; SI-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), !tbaa !1, addrspace 1)
; SI-NEXT: $vgpr0 = COPY [[LOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_LOAD %0 :: (load (s24), align 4, addrspace 1, !tbaa !1)
$vgpr0 = COPY %1
...
|
