1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -march=amdgcn -run-pass=legalizer %s -o - | FileCheck %s
---
name: test
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[C]](p0) :: (load (s32), align 16)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 4
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[C1]](p0) :: (load (s32) from unknown-address + 4)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 8
; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s32) = G_LOAD [[C2]](p0) :: (load (s32) from unknown-address + 8, align 8)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 12
; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[C3]](p0) :: (load (s32) from unknown-address + 12)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[LOAD]](s32), [[LOAD1]](s32), [[LOAD2]](s32), [[LOAD3]](s32)
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[BUILD_VECTOR]](<4 x s32>)
; CHECK-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[BITCAST]](<2 x p0>)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[UV]](p0)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY1]](p0)
; CHECK-NEXT: $vgpr0 = COPY [[UV2]](s32)
; CHECK-NEXT: $vgpr1 = COPY [[UV3]](s32)
; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
%0:_(p0) = G_CONSTANT i64 0
%1:_(<2 x p0>) = G_BUILD_VECTOR %0:_(p0), %0:_(p0)
%2:_(<2 x p0>) = G_LOAD %0:_(p0) :: (load (<2 x p0>))
%3:_(p0) = G_SHUFFLE_VECTOR %2:_(<2 x p0>), %1:_, shufflemask(0)
%4:_(s32), %5:_(s32) = G_UNMERGE_VALUES %3:_(p0)
$vgpr0 = COPY %4:_(s32)
$vgpr1 = COPY %5:_(s32)
SI_RETURN implicit $vgpr0, implicit $vgpr1
...
|
