File: subreg-intervals.mir

package info (click to toggle)
llvm-toolchain-21 1%3A21.1.6-3
  • links: PTS, VCS
  • area: main
  • in suites: sid
  • size: 2,245,028 kB
  • sloc: cpp: 7,619,726; ansic: 1,434,018; asm: 1,058,748; python: 252,740; f90: 94,671; objc: 70,685; lisp: 42,813; pascal: 18,401; sh: 8,601; ml: 5,111; perl: 4,720; makefile: 3,675; awk: 3,523; javascript: 2,409; xml: 892; fortran: 770
file content (32 lines) | stat: -rw-r--r-- 722 bytes parent folder | download | duplicates (9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
# RUN: llc -mtriple=amdgcn -run-pass liveintervals -debug-only=regalloc -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
# RUN: llc -mtriple=amdgcn --passes='print<live-intervals>' -debug-only=regalloc -o /dev/null %s 2>&1 | FileCheck %s
# REQUIRES: asserts

# CHECK: INTERVALS
# CHECK: %0
# CHECK-LABEL: Machine code for function test1:

--- |
  define amdgpu_kernel void @test1() { ret void }
...
---
name: test1
registers:
  - { id: 0, class: sreg_64 }
body: |
  bb.0:
    S_CBRANCH_VCCNZ %bb.1, implicit undef $vcc
    S_BRANCH %bb.2

  bb.1:
    S_NOP 0, implicit-def undef %0.sub0
    S_BRANCH %bb.3

  bb.2:
    S_NOP 0, implicit-def %0
    S_BRANCH %bb.3

  bb.3:
    S_NOP 0
    S_NOP 0, implicit %0
...