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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
;; xvrepl128vei.b
define <32 x i8> @shufflevector_v32i8(<32 x i8> %a, <32 x i8> %b) {
; CHECK-LABEL: shufflevector_v32i8:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrepl128vei.b $xr0, $xr0, 1
; CHECK-NEXT: ret
%c = shufflevector <32 x i8> %a, <32 x i8> %b, <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
ret <32 x i8> %c
}
;; xvrepl128vei.h
define <16 x i16> @shufflevector_v16i16(<16 x i16> %a, <16 x i16> %b) {
; CHECK-LABEL: shufflevector_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrepl128vei.h $xr0, $xr0, 3
; CHECK-NEXT: ret
%c = shufflevector <16 x i16> %a, <16 x i16> %b, <16 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3,
i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11>
ret <16 x i16> %c
}
;; xvrepl128vei.w
define <8 x i32> @shufflevector_v8i32(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: shufflevector_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvpermi.d $xr0, $xr0, 78
; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 3
; CHECK-NEXT: ret
%c = shufflevector <8 x i32> %a, <8 x i32> %b, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 3, i32 3, i32 3, i32 3>
ret <8 x i32> %c
}
;; xvrepl128vei.d
define <4 x i64> @shufflevector_v4i64(<4 x i64> %a, <4 x i64> %b) {
; CHECK-LABEL: shufflevector_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrepl128vei.d $xr0, $xr0, 1
; CHECK-NEXT: ret
%c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
ret <4 x i64> %c
}
;; xvrepl128vei.w
define <8 x float> @shufflevector_v8f32(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: shufflevector_v8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrepl128vei.w $xr0, $xr0, 3
; CHECK-NEXT: ret
%c = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 7, i32 7, i32 7, i32 7>
ret <8 x float> %c
}
;; xvrepl128vei.d
define <4 x double> @shufflevector_v4f64(<4 x double> %a, <4 x double> %b) {
; CHECK-LABEL: shufflevector_v4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: xvrepl128vei.d $xr0, $xr1, 1
; CHECK-NEXT: ret
%c = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 5, i32 5, i32 7, i32 7>
ret <4 x double> %c
}
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