1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
# RUN: llvm-mc -triple=xtensa -mattr=+timers3 -disassemble %s | FileCheck -check-prefixes=CHECK-TIMER %s
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
## Verify that binary code is correctly disassembled with
## Xtensa timer option enabled. Also verify that dissasembling without
## Xtensa timer option generates warnings.
[0x20,0xea,0x61]
#CHECK-INST: xsr a2, ccount
#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0xf0,0x61]
#CHECK-TIMER: xsr a2, ccompare0
#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0xf1,0x61]
#CHECK-TIMER: xsr a2, ccompare1
#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
[0x20,0xf2,0x61]
#CHECK-TIMER: xsr a2, ccompare2
#CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
|
