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|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
define void @test(ptr %p) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[P:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[ARRAYIDX7_US_I_841:%.*]] = getelementptr i8, ptr [[P]], i64 36
; CHECK-NEXT: [[ARRAYIDX7_US_I_1261:%.*]] = getelementptr i8, ptr [[P]], i64 52
; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[ARRAYIDX7_US_I_1261]], align 4
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[TMP19:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> [[TMP19]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr [[ARRAYIDX7_US_I_841]], align 4
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <8 x i32> [[TMP4]], <8 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <12 x i32> [[TMP6]], <12 x i32> [[TMP20]], <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, <16 x i32> [[TMP9]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 18, i32 poison, i32 poison, i32 poison, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <16 x i32> [[TMP10]], i32 [[TMP0]], i32 6
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <16 x i32> [[TMP11]], <16 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 4, i32 6, i32 6, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: [[TMP13:%.*]] = add <16 x i32> [[TMP3]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = srem <16 x i32> [[TMP13]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP15:%.*]] = or <12 x i32> [[TMP7]], zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = srem <12 x i32> [[TMP15]], <i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER_US_I:.*]]
; CHECK: [[FOR_COND1_PREHEADER_US_I]]:
; CHECK-NEXT: [[A_PROMOTED253537_US_I:%.*]] = phi i32 [ [[OP_RDX8:%.*]], %[[FOR_COND1_PREHEADER_US_I]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP14]])
; CHECK-NEXT: [[TMP18:%.*]] = call i32 @llvm.vector.reduce.add.v12i32(<12 x i32> [[TMP16]])
; CHECK-NEXT: [[OP_RDX:%.*]] = add i32 [[TMP18]], [[TMP17]]
; CHECK-NEXT: [[OP_RDX8]] = add i32 [[OP_RDX]], 0
; CHECK-NEXT: br label %[[FOR_COND1_PREHEADER_US_I]]
;
entry:
%arrayidx7.us.i.841 = getelementptr i8, ptr %p, i64 36
%arrayidx7.us.i.946 = getelementptr i8, ptr %p, i64 40
%arrayidx7.us.i.1051 = getelementptr i8, ptr %p, i64 44
%arrayidx7.us.i.1156 = getelementptr i8, ptr %p, i64 48
%arrayidx7.us.i.1261 = getelementptr i8, ptr %p, i64 52
%arrayidx7.us.i.1366 = getelementptr i8, ptr %p, i64 56
%arrayidx7.us.i.1471 = getelementptr i8, ptr %p, i64 60
%arrayidx7.us.i.1576 = getelementptr i8, ptr %p, i64 64
%add8.us.i.1.4 = add i32 0, 0
%rem.us.i.1.4 = srem i32 %add8.us.i.1.4, 1
%add8.us.i.1.5 = add i32 0, 0
%rem.us.i.1.5 = srem i32 %add8.us.i.1.5, 1
%invariant.op91 = add i32 %rem.us.i.1.4, %rem.us.i.1.5
%add8.us.i.1.6 = add i32 0, 0
%rem.us.i.1.6 = srem i32 %add8.us.i.1.6, 1
%invariant.op92 = add i32 %invariant.op91, %rem.us.i.1.6
%0 = load i32, ptr %arrayidx7.us.i.841, align 4
%1 = load i32, ptr %arrayidx7.us.i.946, align 4
%2 = load i32, ptr %arrayidx7.us.i.1051, align 4
%3 = load i32, ptr %arrayidx7.us.i.1156, align 4
%4 = load i32, ptr %arrayidx7.us.i.1261, align 4
%5 = load i32, ptr %arrayidx7.us.i.1366, align 4
%add8.us.i.7.6 = or i32 %5, 0
%rem.us.i.7.6 = srem i32 %add8.us.i.7.6, 1
%6 = load i32, ptr %arrayidx7.us.i.1471, align 4
%add8.us.i.7.7 = or i32 %6, 0
%rem.us.i.7.7 = srem i32 %add8.us.i.7.7, 1
%invariant.op165 = add i32 %rem.us.i.7.6, %rem.us.i.7.7
%7 = load i32, ptr %arrayidx7.us.i.1576, align 4
%add8.us.i.7.8 = or i32 %7, 0
%rem.us.i.7.8 = srem i32 %add8.us.i.7.8, 1
%invariant.op166 = add i32 %invariant.op165, %rem.us.i.7.8
%add8.us.i.8 = or i32 %0, 0
%rem.us.i.8 = srem i32 %add8.us.i.8, 1
%invariant.op167 = add i32 %invariant.op166, %rem.us.i.8
%add8.us.i.8.1 = or i32 %1, 0
%rem.us.i.8.1 = srem i32 %add8.us.i.8.1, 1
%invariant.op168 = add i32 %invariant.op167, %rem.us.i.8.1
%add8.us.i.8.2 = or i32 %2, 0
%rem.us.i.8.2 = srem i32 %add8.us.i.8.2, 1
%invariant.op169 = add i32 %invariant.op168, %rem.us.i.8.2
%add8.us.i.8.3 = or i32 %3, 0
%rem.us.i.8.3 = srem i32 %add8.us.i.8.3, 1
%invariant.op170 = add i32 %invariant.op169, %rem.us.i.8.3
%add8.us.i.8.4 = or i32 %4, 0
%rem.us.i.8.4 = srem i32 %add8.us.i.8.4, 1
%invariant.op171 = add i32 %invariant.op170, %rem.us.i.8.4
%add8.us.i.8.5 = or i32 %5, 0
%rem.us.i.8.5 = srem i32 %add8.us.i.8.5, 1
%invariant.op172 = add i32 %invariant.op171, %rem.us.i.8.5
%add8.us.i.8.6 = or i32 %6, 0
%rem.us.i.8.6 = srem i32 %add8.us.i.8.6, 0
%invariant.op173 = add i32 %invariant.op172, %rem.us.i.8.6
%add8.us.i.8.7 = or i32 %7, 0
%rem.us.i.8.7 = srem i32 %add8.us.i.8.7, 0
%invariant.op174 = add i32 %invariant.op173, %rem.us.i.8.7
%invariant.op181 = add i32 %invariant.op174, 0
%invariant.op182 = add i32 %invariant.op181, 0
%invariant.op183 = add i32 %invariant.op182, 0
%invariant.op184 = add i32 %invariant.op183, 0
%invariant.op185 = add i32 %invariant.op184, 0
%invariant.op186 = add i32 %invariant.op185, 0
%invariant.op187 = add i32 %invariant.op186, 0
%invariant.op188 = add i32 %invariant.op187, 0
%add8.us.i.11.1 = or i32 %4, 0
%rem.us.i.11.1 = srem i32 %add8.us.i.11.1, 1
%invariant.op189 = add i32 %invariant.op188, %rem.us.i.11.1
%add8.us.i.11.2 = add i32 0, 0
%rem.us.i.11.2 = srem i32 %add8.us.i.11.2, 1
%invariant.op190 = add i32 %invariant.op189, %rem.us.i.11.2
%add8.us.i.11.3 = add i32 %6, %2
%rem.us.i.11.3 = srem i32 %add8.us.i.11.3, 1
%invariant.op191 = add i32 %invariant.op190, %rem.us.i.11.3
%add8.us.i.11.4 = add i32 %7, %2
%rem.us.i.11.4 = srem i32 %add8.us.i.11.4, 1
%invariant.op192 = add i32 %invariant.op191, %rem.us.i.11.4
%8 = load i32, ptr %p, align 4
%add8.us.i.12 = add i32 %4, %8
%rem.us.i.12 = srem i32 %add8.us.i.12, 1
%invariant.op193 = add i32 %invariant.op192, %rem.us.i.12
%add8.us.i.12.1 = add i32 %5, %8
%rem.us.i.12.1 = srem i32 %add8.us.i.12.1, 1
%invariant.op194 = add i32 %invariant.op193, %rem.us.i.12.1
%add8.us.i.12.2 = add i32 0, 0
%rem.us.i.12.2 = srem i32 %add8.us.i.12.2, 1
%invariant.op195 = add i32 %invariant.op194, %rem.us.i.12.2
%add8.us.i.12.3 = add i32 0, 0
%rem.us.i.12.3 = srem i32 %add8.us.i.12.3, 1
%invariant.op196 = add i32 %invariant.op195, %rem.us.i.12.3
%add8.us.i.13 = add i32 0, 0
%rem.us.i.13 = srem i32 %add8.us.i.13, 0
%invariant.op197 = add i32 %invariant.op196, %rem.us.i.13
%add8.us.i.13.1 = add i32 0, 0
%rem.us.i.13.1 = srem i32 %add8.us.i.13.1, 0
%invariant.op198 = add i32 %invariant.op197, %rem.us.i.13.1
%add8.us.i.13.2 = add i32 0, 0
%rem.us.i.13.2 = srem i32 %add8.us.i.13.2, 1
%invariant.op199 = add i32 %invariant.op198, %rem.us.i.13.2
%add8.us.i.14 = add i32 0, 0
%rem.us.i.14 = srem i32 %add8.us.i.14, 1
%invariant.op200 = add i32 %invariant.op199, %rem.us.i.14
%add8.us.i.14.1 = add i32 0, 0
%rem.us.i.14.1 = srem i32 %add8.us.i.14.1, 1
%invariant.op201 = add i32 %invariant.op200, %rem.us.i.14.1
%add8.us.i.15 = add i32 0, 0
%rem.us.i.15 = srem i32 %add8.us.i.15, 1
%invariant.op202 = add i32 %invariant.op201, %rem.us.i.15
br label %for.cond1.preheader.us.i
for.cond1.preheader.us.i:
%a.promoted253537.us.i = phi i32 [ %add9.us.i.15.reass, %for.cond1.preheader.us.i ], [ 0, %entry ]
%add9.us.i.15.reass = add i32 %invariant.op92, %invariant.op202
br label %for.cond1.preheader.us.i
}
|
