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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zilsd,+zclsd,+zdinx -simplify-mir \
# RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32 %s
--- |
define void @store_common_value_double(ptr %a, ptr %b, ptr %c, i32 %d, double %e, double %f) #0 {
entry:
store double %f, ptr %a, align 8
store double %f, ptr %b, align 8
store double %f, ptr %c, align 8
ret void
}
define void @store_common_value_double_zero(ptr %a, ptr %b, ptr %c) #0 {
entry:
store double 0.0, ptr %a, align 8
store double 0.0, ptr %b, align 8
store double 0.0, ptr %c, align 8
ret void
}
define void @store_common_ptr_double(double %a, double %b, double %d, ptr %p) #0 {
entry:
store volatile double %a, ptr %p, align 8
store volatile double %b, ptr %p, align 8
store volatile double %b, ptr %p, align 8
ret void
}
define void @load_common_ptr_double(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
entry:
%0 = load double, ptr %g, align 8
%arrayidx1 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 1
%1 = load double, ptr %arrayidx1, align 8
%arrayidx2 = getelementptr inbounds { double, double, i32 }, ptr %g, i32 0, i32 2
%2 = load i32, ptr %arrayidx2, align 8
tail call void @load_common_ptr_double_1(double %0, double %1, i32 %2)
ret void
}
declare void @load_common_ptr_double_1(double, double, double) #0
define void @store_large_offset_double(ptr %p, i32 %dummy, double %a, double %b, double %c) #0 {
entry:
%0 = getelementptr inbounds double, ptr %p, i32 100
store volatile double %a, ptr %0, align 8
%1 = getelementptr inbounds double, ptr %p, i32 101
store volatile double %b, ptr %1, align 8
%2 = getelementptr inbounds double, ptr %p, i32 102
store volatile double %b, ptr %2, align 8
ret void
}
define void @load_large_offset_double(i32 %a, i32 %b, i32 %c, i32 %d, ptr %p) #0 {
entry:
%arrayidx = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 100
%0 = load double, ptr %arrayidx, align 8
%arrayidx1 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 0, i32 101
%1 = load double, ptr %arrayidx1, align 8
%arrayidx2 = getelementptr inbounds { [102 x double], i32 }, ptr %p, i32 0, i32 1
%2 = load i32, ptr %arrayidx2, align 8
tail call void @load_large_offset_double_1(double %0, double %1, i32 %2)
ret void
}
declare void @load_large_offset_double_1(double, double) #0
define void @store_common_value_double_no_opt(ptr %a, i32 %b, double %c, double %d, double %e) #0 {
entry:
store double %e, ptr %a, align 8
ret void
}
define void @store_common_value_double_no_opt2(ptr %a, i32 %b, double %c, double %d, double %e) #0 {
entry:
store volatile double %e, ptr %a, align 8
store volatile double %e, ptr %a, align 8
ret void
}
define void @store_common_ptr_double_no_opt(double %a, i32 %b, i32 %c, i32 %d, i32 %e, ptr %p) #0 {
entry:
store volatile double %a, ptr %p, align 8
ret void
}
define double @load_common_ptr_double_no_opt(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, ptr %g) #0 {
entry:
%0 = load double, ptr %g, align 8
ret double %0
}
define void @store_large_offset_double_no_opt(ptr %p, double %a, double %b) #0 {
entry:
%0 = getelementptr inbounds double, ptr %p, i32 100
store volatile double %a, ptr %0, align 8
%1 = getelementptr inbounds double, ptr %p, i32 101
store volatile double %b, ptr %1, align 8
ret void
}
define { double, double } @load_large_offset_double_no_opt(ptr %p) #0 {
entry:
%arrayidx = getelementptr inbounds double, ptr %p, i32 100
%0 = load double, ptr %arrayidx, align 8
%arrayidx1 = getelementptr inbounds double, ptr %p, i32 101
%1 = load double, ptr %arrayidx1, align 8
%2 = insertvalue { double, double } undef, double %0, 0
%3 = insertvalue { double, double } %2, double %1, 1
ret { double, double } %3
}
attributes #0 = { minsize "target-features"="+zilsd,+zdinx" }
...
---
name: store_common_value_double
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12, $x16, $x17
; RV32-LABEL: name: store_common_value_double
; RV32: liveins: $x10, $x11, $x12, $x16, $x17
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x14 = ADDI $x16, 0
; RV32-NEXT: $x15 = ADDI $x17, 0
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
; RV32-NEXT: SD_RV32 killed $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)
; RV32-NEXT: PseudoRET
SD_RV32 renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
SD_RV32 renamable $x16_x17, killed renamable $x11, 0 :: (store (s64) into %ir.b)
SD_RV32 killed renamable $x16_x17, killed renamable $x12, 0 :: (store (s64) into %ir.c)
PseudoRET
...
---
name: store_common_value_double_zero
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12
; RV32-LABEL: name: store_common_value_double_zero
; RV32: liveins: $x10, $x11, $x12
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x14 = ADDI $x0, 0
; RV32-NEXT: $x15 = ADDI $x0, 0
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x10, 0 :: (store (s64) into %ir.a)
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x11, 0 :: (store (s64) into %ir.b)
; RV32-NEXT: SD_RV32 $x14_x15, killed renamable $x12, 0 :: (store (s64) into %ir.c)
; RV32-NEXT: PseudoRET
SD_RV32 $x0_pair, killed renamable $x10, 0 :: (store (s64) into %ir.a)
SD_RV32 $x0_pair, killed renamable $x11, 0 :: (store (s64) into %ir.b)
SD_RV32 $x0_pair, killed renamable $x12, 0 :: (store (s64) into %ir.c)
PseudoRET
...
---
name: store_common_ptr_double
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16
; RV32-LABEL: name: store_common_ptr_double
; RV32: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x14 = ADDI $x16, 0
; RV32-NEXT: SD_RV32 killed renamable $x10_x11, $x14, 0 :: (volatile store (s64) into %ir.p)
; RV32-NEXT: SD_RV32 renamable $x12_x13, $x14, 0 :: (volatile store (s64) into %ir.p)
; RV32-NEXT: SD_RV32 killed renamable $x12_x13, killed $x14, 0 :: (volatile store (s64) into %ir.p)
; RV32-NEXT: PseudoRET
SD_RV32 killed renamable $x10_x11, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
SD_RV32 renamable $x12_x13, renamable $x16, 0 :: (volatile store (s64) into %ir.p)
SD_RV32 killed renamable $x12_x13, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
PseudoRET
...
---
name: load_common_ptr_double
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x16
; RV32-LABEL: name: load_common_ptr_double
; RV32: liveins: $x16
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x15 = ADDI $x16, 0
; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 0 :: (load (s64) from %ir.g)
; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 8 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: renamable $x14 = LW killed $x15, 16 :: (load (s32) from %ir.arrayidx2, align 8)
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
renamable $x10_x11 = LD_RV32 renamable $x16, 0 :: (load (s64) from %ir.g)
renamable $x12_x13 = LD_RV32 renamable $x16, 8 :: (load (s64) from %ir.arrayidx1)
renamable $x14 = LW killed renamable $x16, 16 :: (load (s32) from %ir.arrayidx2, align 8)
PseudoTAIL target-flags(riscv-call) @load_common_ptr_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
...
---
name: store_large_offset_double
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x12, $x13, $x14, $x15
; RV32-LABEL: name: store_large_offset_double
; RV32: liveins: $x10, $x12, $x13, $x14, $x15
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x11 = ADDI $x10, 768
; RV32-NEXT: SD_RV32 killed renamable $x12_x13, $x11, 32 :: (volatile store (s64) into %ir.0)
; RV32-NEXT: SD_RV32 renamable $x14_x15, $x11, 40 :: (volatile store (s64) into %ir.1)
; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed $x11, 48 :: (volatile store (s64) into %ir.2)
; RV32-NEXT: PseudoRET
SD_RV32 killed renamable $x12_x13, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
SD_RV32 renamable $x14_x15, renamable $x10, 808 :: (volatile store (s64) into %ir.1)
SD_RV32 killed renamable $x14_x15, killed renamable $x10, 816 :: (volatile store (s64) into %ir.2)
PseudoRET
...
---
name: load_large_offset_double
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x14
; RV32-LABEL: name: load_large_offset_double
; RV32: liveins: $x14
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x15 = ADDI $x14, 768
; RV32-NEXT: renamable $x10_x11 = LD_RV32 $x15, 32 :: (load (s64) from %ir.arrayidx)
; RV32-NEXT: renamable $x12_x13 = LD_RV32 $x15, 40 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: renamable $x14 = LW killed $x15, 48 :: (load (s32) from %ir.arrayidx2, align 8)
; RV32-NEXT: PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
renamable $x10_x11 = LD_RV32 renamable $x14, 800 :: (load (s64) from %ir.arrayidx)
renamable $x12_x13 = LD_RV32 renamable $x14, 808 :: (load (s64) from %ir.arrayidx1)
renamable $x14 = LW killed renamable $x14, 816 :: (load (s32) from %ir.arrayidx2, align 8)
PseudoTAIL target-flags(riscv-call) @load_large_offset_double_1, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14
...
---
name: store_common_value_double_no_opt
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x16, $x17
; RV32-LABEL: name: store_common_value_double_no_opt
; RV32: liveins: $x10, $x16, $x17
; RV32-NEXT: {{ $}}
; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
; RV32-NEXT: PseudoRET
SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (store (s64) into %ir.a)
PseudoRET
...
---
name: store_common_value_double_no_opt2
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x16, $x17
; RV32-LABEL: name: store_common_value_double_no_opt2
; RV32: liveins: $x10, $x16, $x17
; RV32-NEXT: {{ $}}
; RV32-NEXT: SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
; RV32-NEXT: SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
; RV32-NEXT: PseudoRET
SD_RV32 renamable $x16_x17, renamable $x10, 0 :: (volatile store (s64) into %ir.a)
SD_RV32 killed renamable $x16_x17, killed renamable $x10, 0 :: (volatile store (s64) into %ir.a)
PseudoRET
...
---
name: store_common_ptr_double_no_opt
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x16
; RV32-LABEL: name: store_common_ptr_double_no_opt
; RV32: liveins: $x10, $x11, $x16
; RV32-NEXT: {{ $}}
; RV32-NEXT: SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
; RV32-NEXT: PseudoRET
SD_RV32 killed renamable $x10_x11, killed renamable $x16, 0 :: (volatile store (s64) into %ir.p)
PseudoRET
...
---
name: load_common_ptr_double_no_opt
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x16
; RV32-LABEL: name: load_common_ptr_double_no_opt
; RV32: liveins: $x16
; RV32-NEXT: {{ $}}
; RV32-NEXT: renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g)
; RV32-NEXT: PseudoRET implicit $x10, implicit $x11
renamable $x10_x11 = LD_RV32 killed renamable $x16, 0 :: (load (s64) from %ir.g)
PseudoRET implicit $x10, implicit $x11
...
---
name: store_large_offset_double_no_opt
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11, $x12, $x13, $x14
; RV32-LABEL: name: store_large_offset_double_no_opt
; RV32: liveins: $x10, $x11, $x12, $x13, $x14
; RV32-NEXT: {{ $}}
; RV32-NEXT: $x15 = ADDI $x14, 0
; RV32-NEXT: $x17 = ADDI $x12, 0
; RV32-NEXT: $x16 = ADDI $x11, 0
; RV32-NEXT: SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
; RV32-NEXT: $x14 = ADDI $x13, 0
; RV32-NEXT: SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
; RV32-NEXT: PseudoRET
$x15 = ADDI $x14, 0
$x17 = ADDI $x12, 0
$x16 = ADDI $x11, 0
SD_RV32 killed renamable $x16_x17, renamable $x10, 800 :: (volatile store (s64) into %ir.0)
$x14 = ADDI $x13, 0
SD_RV32 killed renamable $x14_x15, killed renamable $x10, 808 :: (volatile store (s64) into %ir.1)
PseudoRET
...
---
name: load_large_offset_double_no_opt
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10
; RV32-LABEL: name: load_large_offset_double_no_opt
; RV32: liveins: $x10
; RV32-NEXT: {{ $}}
; RV32-NEXT: renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
; RV32-NEXT: renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
; RV32-NEXT: $x10 = ADDI renamable $x14, 0
; RV32-NEXT: $x11 = ADDI killed renamable $x15, 0
; RV32-NEXT: PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
renamable $x14_x15 = LD_RV32 renamable $x10, 800 :: (load (s64) from %ir.arrayidx)
renamable $x12_x13 = LD_RV32 killed renamable $x10, 808 :: (load (s64) from %ir.arrayidx1)
$x10 = ADDI renamable $x14, 0
$x11 = ADDI killed renamable $x15, 0
PseudoRET implicit $x10, implicit $x11, implicit $x12, implicit $x13
...
|
