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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa,+v,+xtheadmempair' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s
---
name: fcvtmod_w_d
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10
; CHECK-LABEL: name: fcvtmod_w_d
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
; CHECK-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
; CHECK-NEXT: $x10 = COPY [[FCVTMOD_W_D]]
; CHECK-NEXT: PseudoRET
%0:fpr64 = COPY $x10
%1:gpr = nofpexcept FCVTMOD_W_D %0, 1
%2:gpr = ADDIW %1, 0
$x10 = COPY %2
PseudoRET
...
---
name: physreg
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11
; CHECK-LABEL: name: physreg
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = ADDIW %0, 0
$x10 = COPY %1
PseudoRET
...
---
name: vfirst
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $v8
; CHECK-LABEL: name: vfirst
; CHECK: liveins: $x10, $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVFIRST_M_B1_:%[0-9]+]]:gpr = PseudoVFIRST_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
; CHECK-NEXT: $x11 = COPY [[PseudoVFIRST_M_B1_]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
%2:gpr = PseudoVFIRST_M_B1 %0:vr, %1:gprnox0, 0
%3:gpr = ADDIW %2, 0
$x11 = COPY %3
PseudoRET
...
---
name: vcpop
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $v8
; CHECK-LABEL: name: vcpop
; CHECK: liveins: $x10, $v8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[COPY]], [[COPY1]], 0 /* e8 */
; CHECK-NEXT: $x11 = COPY [[PseudoVCPOP_M_B1_]]
; CHECK-NEXT: PseudoRET
%0:vr = COPY $v8
%1:gprnox0 = COPY $x10
%2:gpr = PseudoVCPOP_M_B1 %0:vr, %1:gprnox0, 0
%3:gpr = ADDIW %2, 0
$x11 = COPY %3
PseudoRET
...
---
name: th_lwd
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10
; CHECK-LABEL: name: th_lwd
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD [[COPY]], 2, 3
; CHECK-NEXT: $x10 = COPY %1
; CHECK-NEXT: $x11 = COPY %2
; CHECK-NEXT: PseudoRET
%0:gpr = COPY $x10
early-clobber %1:gpr, early-clobber %2:gpr = TH_LWD %0, 2, 3
%3:gpr = ADDIW %1, 0
%4:gpr = ADDIW %2, 0
$x10 = COPY %3
$x11 = COPY %4
PseudoRET
...
---
name: movgprnox0_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11, $x12, $x13
; CHECK-LABEL: name: movgprnox0_1
; CHECK: liveins: $x10, $x11, $x12, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x13
; CHECK-NEXT: [[PseudoCCMOVGPRNoX0_:%[0-9]+]]:gprnox0 = PseudoCCMOVGPRNoX0 [[COPY]], [[COPY1]], 1, [[COPY2]], [[COPY3]]
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[PseudoCCMOVGPRNoX0_]], 0
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
%3:gpr = COPY $x13
%4:gprnox0 = ADDIW %2, 0
%5:gprnox0 = ADDIW %3, 0
%6:gprnox0 = PseudoCCMOVGPRNoX0 %0, %1, 1, %4, %5
%7:gpr = ADDIW %6, 0
$x10 = COPY %7
PseudoRET implicit $x10
...
---
name: movgprnox0_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11, $x12, $x13
; CHECK-LABEL: name: movgprnox0_2
; CHECK: liveins: $x10, $x11, $x12, $x13
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
; CHECK-NEXT: [[SRAIW:%[0-9]+]]:gprnox0 = SRAIW [[COPY2]], 0
; CHECK-NEXT: [[SRAIW1:%[0-9]+]]:gprnox0 = SRAIW [[COPY3]], 0
; CHECK-NEXT: [[PseudoCCMOVGPRNoX0_:%[0-9]+]]:gprnox0 = PseudoCCMOVGPRNoX0 [[COPY]], [[COPY1]], 1, [[SRAIW]], [[SRAIW1]]
; CHECK-NEXT: $x10 = COPY [[PseudoCCMOVGPRNoX0_]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gpr = COPY $x10
%1:gpr = COPY $x11
%2:gpr = COPY $x12
%3:gpr = COPY $x13
%4:gprnox0 = SRAIW %2, 0
%5:gprnox0 = SRAIW %3, 0
%6:gprnox0 = PseudoCCMOVGPRNoX0 %0, %1, 1, %4, %5
%7:gpr = ADDIW %6, 0
$x10 = COPY %7
PseudoRET implicit $x10
...
---
name: lui_addi_1
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: lui_addi_1
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 11
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI killed [[LUI]], -1756
; CHECK-NEXT: BEQ killed [[ADDIW]], [[ADDI]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW $x0, 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[ADDI]], %bb.0, [[LW]], %bb.1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprtc = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY1]]
; CHECK-NEXT: $x11 = COPY [[PHI]]
; CHECK-NEXT: PseudoTAILIndirect [[COPY1]], csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
bb.0:
liveins: $x10
%2:gpr = COPY $x10
%4:gpr = ADDIW %2, 0
%5:gpr = LUI 11
%3:gpr = ADDI killed %5, -1756
BEQ killed %4, %3, %bb.2
PseudoBR %bb.1
bb.1:
%0:gpr = LW $x0, 0
bb.2:
%1:gpr = PHI %3, %bb.0, %0, %bb.1
%6:gpr = ADDIW %1, 0
%7:gprtc = COPY $x0
$x10 = COPY %7
$x11 = COPY %6
PseudoTAILIndirect %7, csr_ilp32_lp64, implicit $x2, implicit $x10, implicit $x11
...
---
# The sext.w was erroneously removed in an earlier broken version of the patch
# for RISCVOptWInstrs that added lui/addi handling.
name: lui_addi_2
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: lui_addi_2
; CHECK: bb.0.entry:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 524289
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[LUI]], -2048
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`)
; CHECK-NEXT: [[AND:%[0-9]+]]:gpr = AND [[LWU]], [[ADDI]]
; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW killed [[AND]], 0
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: PseudoRET implicit $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-NEXT: %call_target_dummy:gprjalr = COPY $x0
; CHECK-NEXT: PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
; CHECK-NEXT: $x10 = COPY [[LWU]]
; CHECK-NEXT: PseudoRET implicit $x10
bb.0.entry:
%13:gpr = LUI 524289
%14:gpr = ADDI %13, -2048
bb.1:
%1:gpr = LWU $x0, 0 :: (load (s32) from `ptr null`)
%15:gpr = AND %1, %14
%16:gpr = ADDIW killed %15, 0
$x10 = COPY %16
PseudoRET implicit $x10
bb.2:
ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
$x10 = COPY %16
%call_target_dummy:gprjalr = COPY $x0
PseudoCALLIndirect %call_target_dummy, csr_ilp32_lp64, implicit-def $x1, implicit $x10
ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
$x10 = COPY %1
PseudoRET implicit $x10
...
|
