1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs \
; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefixes=CHECK,RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
; RUN: -target-abi lp64f < %s | FileCheck %s -check-prefixes=CHECK,RV64IZFH
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
; RUN: -target-abi lp64 < %s | FileCheck %s -check-prefixes=CHECK,RV64IZHINX
define half @sitofp_i128_to_f16(i128 %a) nounwind {
; RV64I-LABEL: sitofp_i128_to_f16:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floattisf
; RV64I-NEXT: call __truncsfhf2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: sitofp_i128_to_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __floattihf
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: sitofp_i128_to_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: call __floattihf
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
%1 = sitofp i128 %a to half
ret half %1
}
define half @uitofp_i128_to_f16(i128 %a) nounwind {
; RV64I-LABEL: uitofp_i128_to_f16:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floatuntisf
; RV64I-NEXT: call __truncsfhf2
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: uitofp_i128_to_f16:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __floatuntihf
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: uitofp_i128_to_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: call __floatuntihf
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
%1 = uitofp i128 %a to half
ret half %1
}
define i128 @fptosi_f16_to_i128(half %a) nounwind {
; RV64I-LABEL: fptosi_f16_to_i128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: call __fixsfti
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: fptosi_f16_to_i128:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __fixhfti
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: fptosi_f16_to_i128:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: call __fixhfti
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
%1 = fptosi half %a to i128
ret i128 %1
}
define i128 @fptoui_f16_to_i128(half %a) nounwind {
; RV64I-LABEL: fptoui_f16_to_i128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: call __fixunssfti
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: fptoui_f16_to_i128:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: call __fixunshfti
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: fptoui_f16_to_i128:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -16
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: call __fixunshfti
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 16
; RV64IZHINX-NEXT: ret
%1 = fptoui half %a to i128
ret i128 %1
}
define i128 @fptosi_sat_f16_to_i128(half %a) nounwind {
; RV64I-LABEL: fptosi_sat_f16_to_i128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s4, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s5, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: lui a1, 1044480
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixsfti
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv s3, a1
; RV64I-NEXT: li s5, -1
; RV64I-NEXT: bgez s0, .LBB4_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: slli s3, s5, 63
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: lui a1, 520192
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: blez a0, .LBB4_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: srli s3, s5, 1
; RV64I-NEXT: .LBB4_4:
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __unordsf2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: sgtz a1, s4
; RV64I-NEXT: slti a2, s0, 0
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: neg a3, a1
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a1, a0, s3
; RV64I-NEXT: and a2, a2, s1
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s5, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: fptosi_sat_f16_to_i128:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -32
; RV64IZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
; RV64IZFH-NEXT: fcvt.s.h fs0, fa0
; RV64IZFH-NEXT: lui a0, 1044480
; RV64IZFH-NEXT: fmv.w.x fa5, a0
; RV64IZFH-NEXT: fle.s s0, fa5, fs0
; RV64IZFH-NEXT: fmv.s fa0, fs0
; RV64IZFH-NEXT: call __fixsfti
; RV64IZFH-NEXT: li a2, -1
; RV64IZFH-NEXT: bnez s0, .LBB4_2
; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: slli a1, a2, 63
; RV64IZFH-NEXT: .LBB4_2:
; RV64IZFH-NEXT: lui a3, %hi(.LCPI4_0)
; RV64IZFH-NEXT: flw fa5, %lo(.LCPI4_0)(a3)
; RV64IZFH-NEXT: flt.s a3, fa5, fs0
; RV64IZFH-NEXT: beqz a3, .LBB4_4
; RV64IZFH-NEXT: # %bb.3:
; RV64IZFH-NEXT: srli a1, a2, 1
; RV64IZFH-NEXT: .LBB4_4:
; RV64IZFH-NEXT: feq.s a2, fs0, fs0
; RV64IZFH-NEXT: neg a3, a3
; RV64IZFH-NEXT: neg a4, s0
; RV64IZFH-NEXT: neg a2, a2
; RV64IZFH-NEXT: and a0, a4, a0
; RV64IZFH-NEXT: and a1, a2, a1
; RV64IZFH-NEXT: or a0, a3, a0
; RV64IZFH-NEXT: and a0, a2, a0
; RV64IZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 32
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: fptosi_sat_f16_to_i128:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -32
; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: fcvt.s.h s0, a0
; RV64IZHINX-NEXT: lui a0, 1044480
; RV64IZHINX-NEXT: fle.s s1, a0, s0
; RV64IZHINX-NEXT: mv a0, s0
; RV64IZHINX-NEXT: call __fixsfti
; RV64IZHINX-NEXT: li a2, -1
; RV64IZHINX-NEXT: bnez s1, .LBB4_2
; RV64IZHINX-NEXT: # %bb.1:
; RV64IZHINX-NEXT: slli a1, a2, 63
; RV64IZHINX-NEXT: .LBB4_2:
; RV64IZHINX-NEXT: lui a3, 520192
; RV64IZHINX-NEXT: addi a3, a3, -1
; RV64IZHINX-NEXT: flt.s a3, a3, s0
; RV64IZHINX-NEXT: beqz a3, .LBB4_4
; RV64IZHINX-NEXT: # %bb.3:
; RV64IZHINX-NEXT: srli a1, a2, 1
; RV64IZHINX-NEXT: .LBB4_4:
; RV64IZHINX-NEXT: feq.s a2, s0, s0
; RV64IZHINX-NEXT: neg a3, a3
; RV64IZHINX-NEXT: neg a4, s1
; RV64IZHINX-NEXT: neg a2, a2
; RV64IZHINX-NEXT: and a0, a4, a0
; RV64IZHINX-NEXT: and a1, a2, a1
; RV64IZHINX-NEXT: or a0, a3, a0
; RV64IZHINX-NEXT: and a0, a2, a0
; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 32
; RV64IZHINX-NEXT: ret
%1 = tail call i128 @llvm.fptosi.sat.i128.f16(half %a)
ret i128 %1
}
declare i128 @llvm.fptosi.sat.i128.f16(half)
define i128 @fptoui_sat_f16_to_i128(half %a) nounwind {
; RV64I-LABEL: fptoui_sat_f16_to_i128:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __extendhfsf2
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: lui a1, 522240
; RV64I-NEXT: addi a1, a1, -1
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: neg s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: addi s2, a0, -1
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixunssfti
; RV64I-NEXT: and a0, s2, a0
; RV64I-NEXT: and a1, s2, a1
; RV64I-NEXT: or a0, s1, a0
; RV64I-NEXT: or a1, s1, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IZFH-LABEL: fptoui_sat_f16_to_i128:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -32
; RV64IZFH-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: lui a0, %hi(.LCPI5_0)
; RV64IZFH-NEXT: flw fa5, %lo(.LCPI5_0)(a0)
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
; RV64IZFH-NEXT: fmv.w.x fa4, zero
; RV64IZFH-NEXT: fle.s a0, fa4, fa0
; RV64IZFH-NEXT: flt.s a1, fa5, fa0
; RV64IZFH-NEXT: neg s0, a1
; RV64IZFH-NEXT: neg s1, a0
; RV64IZFH-NEXT: call __fixunssfti
; RV64IZFH-NEXT: and a0, s1, a0
; RV64IZFH-NEXT: and a1, s1, a1
; RV64IZFH-NEXT: or a0, s0, a0
; RV64IZFH-NEXT: or a1, s0, a1
; RV64IZFH-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 32
; RV64IZFH-NEXT: ret
;
; RV64IZHINX-LABEL: fptoui_sat_f16_to_i128:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: addi sp, sp, -32
; RV64IZHINX-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
; RV64IZHINX-NEXT: lui a1, 522240
; RV64IZHINX-NEXT: addi a1, a1, -1
; RV64IZHINX-NEXT: fle.s a2, zero, a0
; RV64IZHINX-NEXT: flt.s a1, a1, a0
; RV64IZHINX-NEXT: neg s0, a1
; RV64IZHINX-NEXT: neg s1, a2
; RV64IZHINX-NEXT: call __fixunssfti
; RV64IZHINX-NEXT: and a0, s1, a0
; RV64IZHINX-NEXT: and a1, s1, a1
; RV64IZHINX-NEXT: or a0, s0, a0
; RV64IZHINX-NEXT: or a1, s0, a1
; RV64IZHINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64IZHINX-NEXT: addi sp, sp, 32
; RV64IZHINX-NEXT: ret
%1 = tail call i128 @llvm.fptoui.sat.i128.f16(half %a)
ret i128 %1
}
declare i128 @llvm.fptoui.sat.i128.f16(half)
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}
|
