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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v -run-pass=riscv-vector-peephole \
# RUN: -verify-machineinstrs | FileCheck %s
---
name: avl_not_dominated
body: |
bb.0:
; CHECK-LABEL: name: avl_not_dominated
; CHECK: %evl:gprnox0 = ADDI $x0, 1
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %evl, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: PseudoVSE32_V_M1 %x, $noreg, %evl, 5 /* e32 */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
%evl:gprnox0 = ADDI $x0, 1
PseudoVSE32_V_M1 %x:vr, $noreg, %evl, 5 /* e32 */
...
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