File: isel-extract-subvector-non-pow2-elems.ll

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llvm-toolchain-21 1%3A21.1.7-1
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Ensure assertion is not hit when folding concat of two contiguous extract_subvector operations
; from a source with a non-power-of-two vector length.
; RUN: llc -mtriple=x86_64 -mattr=+avx2 < %s | FileCheck %s

define void @foo(ptr %pDst) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
; CHECK-NEXT:    vmovups %ymm0, 16(%rdi)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
entry:
  %0 = shufflevector <12 x float> zeroinitializer, <12 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %1 = shufflevector <12 x float> zeroinitializer, <12 x float> zeroinitializer, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
  %2 = getelementptr i8, ptr %pDst, i64 16
  %3 = getelementptr i8, ptr %pDst, i64 32
  store <4 x float> %0, ptr %2, align 1
  store <4 x float> %1, ptr %3, align 1
  ret void
}