1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
// RUN: %clang_cc1 %s -O3 -triple=x86_64-apple-darwin -target-feature +bmi -emit-llvm -o - | FileCheck %s
// Don't include mm_malloc.h, it's system specific.
#define __MM_MALLOC_H
#include <x86intrin.h>
// The double underscore intrinsics are for compatibility with
// AMD's BMI interface. The single underscore intrinsics
// are for compatibility with Intel's BMI interface.
// Apart from the underscores, the interfaces are identical
// except in one case: although the 'bextr' register-form
// instruction is identical in hardware, the AMD and Intel
// intrinsics are different!
unsigned short test__tzcnt_u16(unsigned short __X) {
// CHECK: @llvm.cttz.i16
return __tzcnt_u16(__X);
}
unsigned int test__andn_u32(unsigned int __X, unsigned int __Y) {
// CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1
// CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]]
return __andn_u32(__X, __Y);
}
unsigned int test__bextr_u32(unsigned int __X, unsigned int __Y) {
// CHECK: @llvm.x86.bmi.bextr.32
return __bextr_u32(__X, __Y);
}
unsigned int test__blsi_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = sub i32 0, [[SRC:%.*]]
// CHECK-NEXT: %{{.*}} = and i32 [[SRC]], [[DEST]]
return __blsi_u32(__X);
}
unsigned int test__blsmsk_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = add i32 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = xor i32 [[DEST]], [[SRC]]
return __blsmsk_u32(__X);
}
unsigned int test__blsr_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = add i32 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = and i32 [[DEST]], [[SRC]]
return __blsr_u32(__X);
}
unsigned int test__tzcnt_u32(unsigned int __X) {
// CHECK: @llvm.cttz.i32
return __tzcnt_u32(__X);
}
unsigned long long test__andn_u64(unsigned long __X, unsigned long __Y) {
// CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1
// CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]]
return __andn_u64(__X, __Y);
}
unsigned long long test__bextr_u64(unsigned long __X, unsigned long __Y) {
// CHECK: @llvm.x86.bmi.bextr.64
return __bextr_u64(__X, __Y);
}
unsigned long long test__blsi_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = sub i64 0, [[SRC:%.*]]
// CHECK-NEXT: %{{.*}} = and i64 [[SRC]], [[DEST]]
return __blsi_u64(__X);
}
unsigned long long test__blsmsk_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = add i64 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = xor i64 [[DEST]], [[SRC]]
return __blsmsk_u64(__X);
}
unsigned long long test__blsr_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = add i64 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = and i64 [[DEST]], [[SRC]]
return __blsr_u64(__X);
}
unsigned long long test__tzcnt_u64(unsigned long long __X) {
// CHECK: @llvm.cttz.i64
return __tzcnt_u64(__X);
}
// Intel intrinsics
unsigned short test_tzcnt_u16(unsigned short __X) {
// CHECK: @llvm.cttz.i16
return _tzcnt_u16(__X);
}
unsigned int test_andn_u32(unsigned int __X, unsigned int __Y) {
// CHECK: [[DEST:%.*]] = xor i32 %{{.*}}, -1
// CHECK-NEXT: %{{.*}} = and i32 %{{.*}}, [[DEST]]
return _andn_u32(__X, __Y);
}
unsigned int test_bextr_u32(unsigned int __X, unsigned int __Y,
unsigned int __Z) {
// CHECK: @llvm.x86.bmi.bextr.32
return _bextr_u32(__X, __Y, __Z);
}
unsigned int test_blsi_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = sub i32 0, [[SRC:%.*]]
// CHECK-NEXT: %{{.*}} = and i32 [[SRC]], [[DEST]]
return _blsi_u32(__X);
}
unsigned int test_blsmsk_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = add i32 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = xor i32 [[DEST]], [[SRC]]
return _blsmsk_u32(__X);
}
unsigned int test_blsr_u32(unsigned int __X) {
// CHECK: [[DEST:%.*]] = add i32 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = and i32 [[DEST]], [[SRC]]
return _blsr_u32(__X);
}
unsigned int test_tzcnt_u32(unsigned int __X) {
// CHECK: @llvm.cttz.i32
return _tzcnt_u32(__X);
}
unsigned long long test_andn_u64(unsigned long __X, unsigned long __Y) {
// CHECK: [[DEST:%.*]] = xor i64 %{{.*}}, -1
// CHECK-NEXT: %{{.*}} = and i64 %{{.*}}, [[DEST]]
return _andn_u64(__X, __Y);
}
unsigned long long test_bextr_u64(unsigned long __X, unsigned int __Y,
unsigned int __Z) {
// CHECK: @llvm.x86.bmi.bextr.64
return _bextr_u64(__X, __Y, __Z);
}
unsigned long long test_blsi_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = sub i64 0, [[SRC:%.*]]
// CHECK-NEXT: %{{.*}} = and i64 [[SRC]], [[DEST]]
return _blsi_u64(__X);
}
unsigned long long test_blsmsk_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = add i64 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = xor i64 [[DEST]], [[SRC]]
return _blsmsk_u64(__X);
}
unsigned long long test_blsr_u64(unsigned long long __X) {
// CHECK: [[DEST:%.*]] = add i64 [[SRC:%.*]], -1
// CHECK-NEXT: %{{.*}} = and i64 [[DEST]], [[SRC]]
return _blsr_u64(__X);
}
unsigned long long test_tzcnt_u64(unsigned long long __X) {
// CHECK: @llvm.cttz.i64
return _tzcnt_u64(__X);
}
|
