1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74
  
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      ; RUN: llc -O1 < %s -mtriple=armv7 -mattr=+db | FileCheck %s
@x1 = global i32 0, align 4
@x2 = global i32 0, align 4
define void @test() {
entry:
  br label %for.body
for.body:                                         ; preds = %for.body, %entry
  %i.013 = phi i32 [ 1, %entry ], [ %inc6, %for.body ]
  store atomic i32 %i.013, i32* @x1 seq_cst, align 4
  store atomic i32 %i.013, i32* @x1 seq_cst, align 4
  store atomic i32 %i.013, i32* @x2 seq_cst, align 4
  %inc6 = add nsw i32 %i.013, 1
  %exitcond = icmp eq i32 %inc6, 2
  br i1 %exitcond, label %for.end, label %for.body
for.end:                                          ; preds = %for.body
  ret void
; The for.body contains 3 seq_cst stores.
; Hence it should have 3 dmb;str;dmb sequences with the middle dmbs collapsed
; CHECK: %for.body
; CHECK-NOT: str
; CHECK: dmb
; CHECK-NOT: dmb
; CHECK: str
; CHECK-NOT: str
; CHECK: dmb
; CHECK-NOT: dmb
; CHECK: str
; CHECK-NOT: str
; CHECK: dmb
; CHECK-NOT: dmb
; CHECK: str
; CHECK-NOT: str
; CHECK: dmb
; CHECK-NOT: dmb
; CHECK-NOT: str
; CHECK: %for.end
}
define void @test2() {
  call void @llvm.arm.dmb(i32 11)
  tail call void @test()
  call void @llvm.arm.dmb(i32 11)
  ret void
; the call should prevent the two dmbs from collapsing
; CHECK: test2:
; CHECK: dmb
; CHECK-NEXT: bl
; CHECK-NEXT: dmb
}
define void @test3() {
  call void @llvm.arm.dmb(i32 11)
  call void @llvm.arm.dsb(i32 9)
  call void @llvm.arm.dmb(i32 11)
  ret void
; the call should prevent the two dmbs from collapsing
; CHECK: test3:
; CHECK: dmb
; CHECK-NEXT: dsb
; CHECK-NEXT: dmb
}
declare void @llvm.arm.dmb(i32)
declare void @llvm.arm.dsb(i32)
 
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