1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
|
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -verify-machineinstrs \
; RUN: -aarch64-atomic-cfg-tidy=0 -disable-cgp -disable-branch-fold \
; RUN: < %s | FileCheck %s
;
; Verify that we don't mess up vector comparisons in fast-isel.
;
define <2 x i32> @icmp_v2i32(<2 x i32> %a) {
; CHECK-LABEL: icmp_v2i32:
; CHECK: ; BB#0:
; CHECK-NEXT: cmeq.2s [[CMP:v[0-9]+]], v0, #0
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
%c = icmp eq <2 x i32> %a, zeroinitializer
br label %bb2
bb2:
%z = zext <2 x i1> %c to <2 x i32>
ret <2 x i32> %z
}
define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
; CHECK-LABEL: icmp_constfold_v2i32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]]
; CHECK-NEXT: ret
%1 = icmp eq <2 x i32> %a, %a
br label %bb2
bb2:
%2 = zext <2 x i1> %1 to <2 x i32>
ret <2 x i32> %2
}
define <4 x i32> @icmp_v4i32(<4 x i32> %a) {
; CHECK-LABEL: icmp_v4i32:
; CHECK: ; BB#0:
; CHECK-NEXT: cmeq.4s [[CMP:v[0-9]+]], v0, #0
; CHECK-NEXT: xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]]
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]]
; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
; CHECK-NEXT: ret
%c = icmp eq <4 x i32> %a, zeroinitializer
br label %bb2
bb2:
%z = zext <4 x i1> %c to <4 x i32>
ret <4 x i32> %z
}
define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
; CHECK-LABEL: icmp_constfold_v4i32:
; CHECK: ; BB#0:
; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]]
; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
; CHECK-NEXT: ret
%1 = icmp eq <4 x i32> %a, %a
br label %bb2
bb2:
%2 = zext <4 x i1> %1 to <4 x i32>
ret <4 x i32> %2
}
define <16 x i8> @icmp_v16i8(<16 x i8> %a) {
; CHECK-LABEL: icmp_v16i8:
; CHECK: ; BB#0:
; CHECK-NEXT: cmeq.16b [[CMP:v[0-9]+]], v0, #0
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
%c = icmp eq <16 x i8> %a, zeroinitializer
br label %bb2
bb2:
%z = zext <16 x i1> %c to <16 x i8>
ret <16 x i8> %z
}
define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
; CHECK-LABEL: icmp_constfold_v16i8:
; CHECK: ; BB#0:
; CHECK-NEXT: movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff
; CHECK-NEXT: ; BB#1:
; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1
; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]]
; CHECK-NEXT: ret
%1 = icmp eq <16 x i8> %a, %a
br label %bb2
bb2:
%2 = zext <16 x i1> %1 to <16 x i8>
ret <16 x i8> %2
}
|
