1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
; RUN: llc < %s -march=xcore | FileCheck %s
define void @_Z1fz(...) {
entry:
; CHECK-LABEL: _Z1fz:
; CHECK: extsp 3
; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}}
; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}}
; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}}
; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}}
; CHECK: ldaw sp, sp[3]
; CHECK: retsp 0
ret void
}
declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind
declare void @f(i32) nounwind
define void @test_vararg(...) nounwind {
entry:
; CHECK-LABEL: test_vararg
; CHECK: extsp 6
; CHECK: stw lr, sp[1]
; CHECK-DAG: stw r3, sp[6]
; CHECK-DAG: stw r0, sp[3]
; CHECK-DAG: stw r1, sp[4]
; CHECK-DAG: stw r2, sp[5]
; CHECK: ldaw r0, sp[3]
; CHECK: stw r0, sp[2]
%list = alloca i8*, align 4
%list1 = bitcast i8** %list to i8*
call void @llvm.va_start(i8* %list1)
br label %for.cond
; CHECK-LABEL: .LBB1_1
; CHECK: ldw r0, sp[2]
; CHECK: add r1, r0, 4
; CHECK: stw r1, sp[2]
; CHECK: ldw r0, r0[0]
; CHECK: bl f
; CHECK: bu .LBB1_1
for.cond:
%0 = va_arg i8** %list, i32
call void @f(i32 %0)
br label %for.cond
call void @llvm.va_end(i8* %list1)
ret void
}
|
