1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
|
# RUN: llc -mtriple x86_64-- -verify-machineinstrs -run-pass branch-folder -o - %s | FileCheck %s
# Check the TCRETURNdi64cc optimization.
--- |
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
define i64 @test(i64 %arg, i8* %arg1) optsize {
%tmp = icmp ult i64 %arg, 100
br i1 %tmp, label %1, label %4
%tmp3 = icmp ult i64 %arg, 10
br i1 %tmp3, label %2, label %3
%tmp5 = tail call i64 @f1(i8* %arg1, i64 %arg)
ret i64 %tmp5
%tmp7 = tail call i64 @f2(i8* %arg1, i64 %arg)
ret i64 %tmp7
ret i64 123
}
declare i64 @f1(i8*, i64)
declare i64 @f2(i8*, i64)
...
---
name: test
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
- { reg: '$rsi' }
body: |
bb.0:
successors: %bb.1, %bb.4
liveins: $rdi, $rsi
$rax = COPY $rdi
CMP64ri8 $rax, 99, implicit-def $eflags
JA_1 %bb.4, implicit $eflags
JMP_1 %bb.1
; CHECK: bb.1:
; CHECK-NEXT: successors: %bb.2({{[^)]+}}){{$}}
; CHECK-NEXT: liveins: $rax, $rsi
; CHECK-NEXT: {{^ $}}
; CHECK-NEXT: $rdi = COPY $rsi
; CHECK-NEXT: $rsi = COPY $rax
; CHECK-NEXT: CMP64ri8 $rax, 9, implicit-def $eflags
; CHECK-NEXT: TCRETURNdi64cc @f1, 0, 3, csr_64, implicit $rsp, implicit $eflags, implicit $ssp, implicit $rsp, implicit $rdi, implicit $rsi, implicit $rdi, implicit-def $rdi, implicit $hsi, implicit-def $hsi, implicit $sih, implicit-def $sih, implicit $sil, implicit-def $sil, implicit $si, implicit-def $si, implicit $esi, implicit-def $esi, implicit $rsi, implicit-def $rsi, implicit $hdi, implicit-def $hdi, implicit $dih, implicit-def $dih, implicit $dil, implicit-def $dil, implicit $di, implicit-def $di, implicit $edi, implicit-def $edi
bb.1:
successors: %bb.2, %bb.3
liveins: $rax, $rsi
CMP64ri8 $rax, 9, implicit-def $eflags
JA_1 %bb.3, implicit $eflags
JMP_1 %bb.2
bb.2:
liveins: $rax, $rsi
$rdi = COPY $rsi
$rsi = COPY $rax
TCRETURNdi64 @f1, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
; CHECK: bb.2:
; CHECK-NEXT: liveins: $rdi, $rsi
; CHECK-NEXT: {{^ $}}
; CHECK-NEXT: TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
bb.3:
liveins: $rax, $rsi
$rdi = COPY $rsi
$rsi = COPY $rax
TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
bb.4:
dead $eax = MOV32ri64 123, implicit-def $rax
RET 0, $rax
...
|
