1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsws:
; CHECK: fcvtas x0, s0
; CHECK: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmsxs:
; CHECK: fcvtas x0, s0
; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i64 @llvm.llround.f32(float %x)
ret i64 %0
}
; CHECK-LABEL: testmswd:
; CHECK: fcvtas x0, d0
; CHECK: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmsxd:
; CHECK: fcvtas x0, d0
; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i64 @llvm.llround.f64(double %x)
ret i64 %0
}
; CHECK-LABEL: testmswl:
; CHECK: bl llroundl
define i32 @testmswl(fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}
; CHECK-LABEL: testmsll:
; CHECK: b llroundl
define i64 @testmsll(fp128 %x) {
entry:
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
ret i64 %0
}
declare i64 @llvm.llround.f32(float) nounwind readnone
declare i64 @llvm.llround.f64(double) nounwind readnone
declare i64 @llvm.llround.f128(fp128) nounwind readnone
|
