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# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
---
name: cvt_pkrtz
legalized: true
regBankSelected: true
# GCN-LABEL: name: cvt_pkrtz
body: |
bb.0:
liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
; GCN: [[SGPR0:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
%0:sgpr(s32) = COPY $sgpr0
; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr0
; GCN: [[VGPR1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr1
%3:vgpr(p1) = COPY $vgpr3_vgpr4
; cvt_pkrtz vs
; GCN: V_CVT_PKRTZ_F16_F32_e64 0, [[VGPR0]], 0, [[SGPR0]]
%4:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %0
; cvt_pkrtz sv
; GCN: V_CVT_PKRTZ_F16_F32_e64 0, [[SGPR0]], 0, [[VGPR0]]
%5:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
; cvt_pkrtz vv
; GCN: V_CVT_PKRTZ_F16_F32_e64 0, [[VGPR0]], 0, [[VGPR1]]
%6:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %1, %2
%7:vgpr(s32) = G_BITCAST %4
%8:vgpr(s32) = G_BITCAST %5
%9:vgpr(s32) = G_BITCAST %6
S_ENDPGM 0, implicit %7, implicit %8, implicit %9
...
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