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|
# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
# CHECK: for.body:
# CHECK-NOT: t2DLS
# CHECK-NOT: t2LEUpdate
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-unknown-unknown"
define dso_local arm_aapcscc void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) local_unnamed_addr {
entry:
%cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
for.body.preheader: ; preds = %entry
br label %for.body
for.cond.cleanup: ; preds = %for.end, %entry
ret void
for.body: ; preds = %for.body.preheader, %for.end
%lsr.iv4 = phi i32* [ %b, %for.body.preheader ], [ %scevgep5, %for.end ]
%lsr.iv2 = phi i32* [ %c, %for.body.preheader ], [ %scevgep3, %for.end ]
%lsr.iv1 = phi i32* [ %a, %for.body.preheader ], [ %scevgep, %for.end ]
%lsr.iv = phi i32 [ %N, %for.body.preheader ], [ %lsr.iv.next, %for.end ]
%size = call i32 @llvm.arm.space(i32 3072, i32 undef)
%0 = load i32, i32* %lsr.iv4, align 4, !tbaa !3
%1 = load i32, i32* %lsr.iv2, align 4, !tbaa !3
%mul = mul nsw i32 %1, %0
store i32 %mul, i32* %lsr.iv1, align 4, !tbaa !3
%cmp = icmp ne i32 %0, 0
br i1 %cmp, label %middle.block, label %for.end
middle.block: ; preds = %for.body
%div = udiv i32 %1, %0
store i32 %div, i32* %lsr.iv1, align 4, !tbaa !3
%size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef)
br label %for.end
for.end: ; preds = %middle.block, %for.body
%lsr.iv.next = add i32 %lsr.iv, -1
%scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
%scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 1
%scevgep5 = getelementptr i32, i32* %lsr.iv4, i32 1
%exitcond = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond, label %for.cond.cleanup, label %for.body
}
declare i32 @llvm.arm.space(i32, i32) #1
attributes #1 = { nounwind }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"min_enum_size", i32 4}
!2 = !{!"clang version 9.0.0 (http://llvm.org/git/clang.git a9c7c0fc5d468f3d18a5c6beb697ab0d5be2ff4c) (http://llvm.org/git/llvm.git f34bff0c141a04a5182d57e2cfb1e4bc582c81b0)"}
!3 = !{!4, !4, i64 0}
!4 = !{!"int", !5, i64 0}
!5 = !{!"omnipotent char", !6, i64 0}
!6 = !{!"Simple C/C++ TBAA"}
...
---
name: size_limit
alignment: 1
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: false
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 16
offsetAdjustment: -8
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants: []
machineFunctionInfo: {}
body: |
bb.0.entry:
successors: %bb.1(0x30000000), %bb.3(0x50000000)
frame-setup tPUSH 14, $noreg, killed $r4, killed $r6, $r7, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 16
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r7, -8
frame-setup CFI_INSTRUCTION offset $r6, -12
frame-setup CFI_INSTRUCTION offset $r4, -16
$r7 = frame-setup tADDrSPi $sp, 2, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
tCBNZ $r3, %bb.3
bb.1.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $r6, def $r7, def $pc
bb.2.for.end:
successors: %bb.1(0x04000000), %bb.3(0x7c000000)
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
renamable $r3, $cpsr = tSUBi8 killed renamable $r3, 1, 14, $noreg
tBcc %bb.1, 0, killed $cpsr
bb.3.for.body:
successors: %bb.4(0x50000000), %bb.2(0x30000000)
dead renamable $r12 = SPACE 3072, undef renamable $r0
renamable $r12 = t2LDRi12 renamable $r1, 0, 14, $noreg :: (load 4 from %ir.lsr.iv4, !tbaa !3)
renamable $lr = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load 4 from %ir.lsr.iv2, !tbaa !3)
t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr
renamable $r4 = nsw t2MUL renamable $lr, renamable $r12, 14, $noreg
tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1, !tbaa !3)
t2Bcc %bb.2, 0, killed $cpsr
bb.4.middle.block:
successors: %bb.2(0x80000000)
renamable $r4 = t2UDIV killed renamable $lr, killed renamable $r12, 14, $noreg
tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store 4 into %ir.lsr.iv1, !tbaa !3)
dead renamable $r4 = SPACE 1024, undef renamable $r0
t2B %bb.2, 14, $noreg
...
|
