1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
; ModuleID = 'sdiv.ll'
source_filename = "sdiv.ll"
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define i8 @test_sdiv_i8(i8 %arg1, i8 %arg2) {
%res = sdiv i8 %arg1, %arg2
ret i8 %res
}
define i16 @test_sdiv_i16(i16 %arg1, i16 %arg2) {
%res = sdiv i16 %arg1, %arg2
ret i16 %res
}
define i32 @test_sdiv_i32(i32 %arg1, i32 %arg2) {
%res = sdiv i32 %arg1, %arg2
ret i32 %res
}
...
---
name: test_sdiv_i8
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_sdiv_i8
; CHECK: liveins: $edi, $esi
; CHECK: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: [[COPY2:%[0-9]+]]:gr32_abcd = COPY $esi
; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
; CHECK: $ax = MOVSX16rr8 [[COPY1]]
; CHECK: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $al
; CHECK: $al = COPY [[COPY4]]
; CHECK: RET 0, implicit $al
%2:gpr(s32) = COPY $edi
%0:gpr(s8) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
%1:gpr(s8) = G_TRUNC %3(s32)
%4:gpr(s8) = G_SDIV %0, %1
$al = COPY %4(s8)
RET 0, implicit $al
...
---
name: test_sdiv_i16
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
- { id: 4, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_sdiv_i16
; CHECK: liveins: $edi, $esi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
; CHECK: $ax = COPY [[COPY1]]
; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax
; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
; CHECK: $ax = COPY [[COPY4]]
; CHECK: RET 0, implicit $ax
%2:gpr(s32) = COPY $edi
%0:gpr(s16) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
%1:gpr(s16) = G_TRUNC %3(s32)
%4:gpr(s16) = G_SDIV %0, %1
$ax = COPY %4(s16)
RET 0, implicit $ax
...
---
name: test_sdiv_i32
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: test_sdiv_i32
; CHECK: liveins: $edi, $esi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; CHECK: $eax = COPY [[COPY]]
; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $eax
; CHECK: $eax = COPY [[COPY2]]
; CHECK: RET 0, implicit $eax
%0:gpr(s32) = COPY $edi
%1:gpr(s32) = COPY $esi
%2:gpr(s32) = G_SDIV %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax
...
|
