File: cortex-a57-misched-vstm.ll

package info (click to toggle)
llvm-toolchain-snapshot 1%3A22~%2B%2B20250731080150%2Bbe449d6b6587-1~exp1
  • links: PTS, VCS
  • area: main
  • in suites: experimental
  • size: 2,250,472 kB
  • sloc: cpp: 7,641,756; ansic: 1,439,220; asm: 1,072,591; python: 253,178; f90: 95,173; objc: 70,722; lisp: 44,365; pascal: 18,720; sh: 10,051; ml: 5,111; perl: 4,720; awk: 3,523; makefile: 3,397; javascript: 2,272; xml: 892; fortran: 783
file content (23 lines) | stat: -rw-r--r-- 666 bytes parent folder | download | duplicates (19) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
 
; REQUIRES: asserts
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -mattr=use-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s

; CHECK:       ********** MI Scheduling **********
; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
; CHECK:       ********** MI Scheduling **********
; CHECK:       schedule starting
; CHECK:       VSTMDIA
; CHECK:       rdefs left
; CHECK-NEXT:  Latency            : 2

%bigVec = type [2 x double]

@var = global %bigVec zeroinitializer

define void @bar(ptr %ptr) {

  %tmp = load %bigVec, ptr %ptr
  store %bigVec %tmp, ptr @var

  ret void
}