File: XCore.td

package info (click to toggle)
llvm 2.6-9.1
  • links: PTS
  • area: main
  • in suites: squeeze
  • size: 57,604 kB
  • ctags: 44,336
  • sloc: cpp: 344,766; sh: 12,407; ansic: 10,617; ada: 3,070; ml: 2,505; perl: 2,496; makefile: 1,426; pascal: 1,163; exp: 389; asm: 307; python: 298; objc: 260; lisp: 182; csh: 117; xml: 38; f90: 36; tcl: 20
file content (62 lines) | stat: -rw-r--r-- 2,192 bytes parent folder | download | duplicates (3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
//===- XCore.td - Describe the XCore Target Machine --------*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Target-independent interfaces which we are implementing
//===----------------------------------------------------------------------===//

include "llvm/Target/Target.td"

//===----------------------------------------------------------------------===//
// Descriptions
//===----------------------------------------------------------------------===//

include "XCoreRegisterInfo.td"
include "XCoreInstrInfo.td"
include "XCoreCallingConv.td"

def XCoreInstrInfo : InstrInfo {
  let TSFlagsFields = [];
  let TSFlagsShifts = [];
}

//===----------------------------------------------------------------------===//
// XCore Subtarget features.
//===----------------------------------------------------------------------===//

def FeatureXS1A
  : SubtargetFeature<"xs1a", "IsXS1A", "true",
                     "Enable XS1A instructions">;

def FeatureXS1B
  : SubtargetFeature<"xs1b", "IsXS1B", "true",
                     "Enable XS1B instructions">;

//===----------------------------------------------------------------------===//
// XCore processors supported.
//===----------------------------------------------------------------------===//

class Proc<string Name, list<SubtargetFeature> Features>
 : Processor<Name, NoItineraries, Features>;

def : Proc<"generic",      [FeatureXS1A]>;
def : Proc<"xs1a-generic", [FeatureXS1A]>;
def : Proc<"xs1b-generic", [FeatureXS1B]>;

//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//

def XCore : Target {
  // Pull in Instruction Info:
  let InstructionSet = XCoreInstrInfo;
}