File: ext2sim.1

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.TH EXT2SIM 1
.UC 4
.SH NAME
ext2sim \- convert hierarchical \fIext\fR\|(5) extracted-circuit files
to flat \fIsim\fR\|(5) files
.SH SYNOPSIS
.B ext2sim
[
.B \-a
.I aliasfile
] [
.B \-l
.I labelsfile
] [
.B \-o
.I simfile
] [
.B \-A
] [
.B \-B
] [
.B \-F
] [
.B \-L
] [
.B \-t
] [
.I "extcheck-options"
] [
.I -y num
] [
.I -f mit|lbl|su
] [
.I -J hier|flat
] [
.I -j  device:sdRclass[/subRclass]/defaultSubstrate
]
.I root

.SH DESCRIPTION
Ext2sim will convert an extracted circuit from the hierarchical
\fIext\fR\|(5) representation produced by Magic to the
flat \fIsim\fR\|(5) representation required by many simulation tools.
The root of the tree to be extracted is the file \fIroot\fB.ext\fR;
it and all the files it references are recursively flattened.
The result is a single, flat representation of the circuit that is
written to the file \fIroot\fB.sim\fR, a list of node aliases
written to the file \fIroot\fB.al\fR, and a list of the locations
of all nodenames in CIF format, suitable for plotting, to the
file \fIroot\fB.nodes\fR.
The file \fIroot\fB.sim\fR is
suitable for use with programs such as
\fIcrystal\fP\|(1), \fIesim\fP\|(1), or \fIsim2spice\fP\|(1).
.LP
The following options are recognized:
.TP 1.0i
.B \-a\ \fIaliasfile\fP
Instead of leaving node aliases in the file \fIroot\fB.al\fR, leave it
in \fIaliasfile\fP.
.TP 1.0i
.B \-l\ \fIlabelfile\fP
Instead of leaving a CIF file with the locations of all node names
in the file \fIroot\fB.nodes\fR, leave it in \fIlabelfile\fP.
.TP 1.0i
.B \-o\ \fIoutfile\fP
Instead of leaving output in the file \fIroot\fB.sim\fR, leave it
in \fIoutfile\fP.
.TP 1.0i
.B \-A
Don't produce the aliases file.
.TP 1.0i
.B \-B
Don't output transistor or node attributes in the \fB.sim\fR file.
This option will also disable the output of information such as
the area and perimeter of source and drain diffusion and the
fet substrate. For compatibitlity reasons the latest version of ext2sim
outputs this information as node attributes.
This option is necessary when preparing input for programs that
don't know about attributes, such as \fIsim2spice\fR\|(1) (which is
actually made obsolete by \fIext2spice\fR\|(1), anyway),
or \fIrsim\fR\|(1).
.TP 1.0i
.B \-F
Don't output nodes that aren't connected to fets (floating nodes).
.TP 1.0i
.B \-L
Don't produce the label file.
.TP 1.0i
.B \-t\fIchar\fR
Trim characters from node names when writing the output file.
\fIChar\fR
should be either "#" or "!".
The option may be used twice if both characters
are desired.
.TP 1.0i
.B \-f \fIMIT|LBL|SU\fR
Select the output format. MIT is the traditional \fIsim\fR(5) format.
LBL is a variant of it understood by \fIgemini\fR(1) which includes the
substrate connection as a fourth terminal before length and width.
SU is the internal Stanford format which is described also in \fIsim\fR(5)
and includes areas and perimeters of fet sources, drains and substrates.
.TP 1.0i
.B \-y \fInum\fR
Select the precision for outputting capacitors. The default is 1 which means
that the capacitors will be printed to a precision of .1 fF.
.TP 1.0i
.B \-J \fIhier|flat\fR
Select the source/drain area and perimeter extraction algorithm. If
\fIhier\fR is selected then the areas and perimeters are extracted
\fIonly within each subcell\fR. For each fet in a subcell the area
and perimeter of its source and drain within this subcell are output.
If two or more fets share a source/drain node then the total area and
perimeter will be output in only one of them and the other will have 0.
If \fIflat\fR is selected the same rules apply only that the scope of
search for area and perimeter is the whole netlist. In general \fIflat\fR
(which is the default) will give accurate results (it will take into
account shared sources/drains) but hier is provided for backwards
compatibility with version 6.4.5. On top of this selection you can
individually control how a terminal of a specific fet will be extracted
if you put a source/drain attribute. \fIext:aph\fR makes the extraction
for that specific terminal hierarchical and \fIext:apf\fR makes the
extraction flat (see the magic tutorial about attaching attribute labels).
Additionally to ease extraction of bipolar transistors the gate attribute
\fIext:aps\fR forces the output of the substrate area and perimeter for
a specific fet (in flat mode only).
.TP 1.0i
.B \-j  \fIdevice:sdRclass[/subRclass]/defaultSubstrate\fR
Gives ext2sim information about the source/drain resistance class of the
fet type \fIdevice\fR. Makes \fIdevice\fR to have \fIsdRclass\fR source
drain resistance class, \fIsubRclass\fR substrate (well) resistance class
and the node named \fIdefaultSubstrate\fR as its default substrate.
The defaults are nfet:0/Gnd\! and pfet:1/6/Vdd\! which correspond to the
MOSIS technology file but things might vary in your site. Ask your local
cad administrator.

.PP
The way the extraction of node area and perimeter works in magic the total
area and perimeter of the source/drain junction is summed up on a single node.
That is why all the junction areas and perimeters are summed up on a single
node (this should not affect simulation results however).
.PP
\fISpecial care must be taken when the substrate of a fet is tied to a
node other than the default substrate\fR (eg in a bootstraping charge
pump).
To get the correct substrate info in these cases the fet(s) with
separate wells should be in their own separate subcell with ext:aph attributes
attached to their sensitive terminals (also all the transistors which share
sensitive terminals with these should be in another subcell with the same
attributes).


.PP
In addition, all of the options of \fIextcheck\fR\|(1) are accepted.

.SH "SCALING AND UNITS"
If all of the \fB.ext\fR files in the tree read by \fIext2sim\fP have the
same geometrical scale (specified in the \fBscale\fP
line in each \fB.ext\fR file),
this scale is reflected through to the output, resulting in substantially
smaller \fB.sim\fR files.
Otherwise, the geometrical unit in the output \fB.sim\fR file
is a centimicron.
.PP
Resistance and capacitance are always output in ohms and femptofarads,
respectively.

.SH "SEE ALSO"
extcheck\|(1), ext2dlys\|(1), ext2spice\|(1),
magic\|(1), rsim\|(1), ext\|(5), sim\|(5)

.SH AUTHOR
Walter Scott additions/fixes by Stefanos Sidiropoulos.

.SH BUGS
Transistor gate capacitance is typically not included in node
capacitances, as most analysis tools compute the gate capacitance directly
from the gate area.
The \fB-c\fR flag therefore provides a limit only on non-gate capacitance.
The areas and perimeters of fet sources and drains work only with the
simple extraction algorithm and not with the extresis flow. So you have
to model them as linear capacitors (create a special extraction style)
if you want to extract parasitic resistances with extresis.