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\section{Optimizations for VLIW/EPIC Architectures}
\subsection{Overview}
Many newer architectures such as the upcoming IA-64 and the
DSPs such as the C6 are VLIW or so called EPIC machines.
These architectures depends on the compiler to
extract instruction level parallelism (\newdef{ILP})
and data level parallelism (\newdef{DLP}).
Optimizations for these architectures include:
\begin{itemize}
\item Hyperblock construction
\item Predication and predicate analysis
\item Hyperblock scheduling
\item Modulo scheduling
\end{itemize}
\subsection{Hyperblocks}
\subsection{Predicate Analysis}
\subsection{Hyperblock Scheduling}
\subsection{Modulo Scheduling}
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