File: alphaRegAlloc.sml

package info (click to toggle)
mlton 20210117%2Bdfsg-3
  • links: PTS, VCS
  • area: main
  • in suites: sid
  • size: 58,464 kB
  • sloc: ansic: 27,682; sh: 4,455; asm: 3,569; lisp: 2,879; makefile: 2,347; perl: 1,169; python: 191; pascal: 68; javascript: 7
file content (81 lines) | stat: -rw-r--r-- 2,191 bytes parent folder | download | duplicates (6)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
(* alphaRegAlloc.sml --- alpha integer and floating register allocator
 *
 * COPYRIGHT (c) 1996 AT&T Bell Laboratories.
 *
 *)

(* Integer and floating register allocators are a partial application
 * of a curried functor. 
 *)



functor AlphaRegAlloc(structure I : INSTRUCTIONS where C = AlphaCells
			structure P : INSN_PROPERTIES where I = I
			structure F : FLOWGRAPH where I = I 
			structure Asm : INSTRUCTION_EMITTER 
			  where I = I and P = F.P) :
   sig
    functor IntRa (structure RaUser : RA_USER_PARAMS
		     where I = I
		     where type B.name = F.B.name
		     (* should be: where I = I -- bug 1205 *)) : RA
    functor FloatRa (structure RaUser : RA_USER_PARAMS
		       where I = I
		       where type B.name = F.B.name
		       (* should be: where I = I *)) : RA
   end =
struct
  structure C = I.C
    (* liveness analysis for general purpose registers *)
  structure RegLiveness =
    Liveness(structure Flowgraph=F
	     structure Instruction=I
	     val defUse = P.defUse C.GP
	     val regSet = C.getCell C.GP 
             val cellset = C.updateCell C.GP)


  (* integer register allocator *)
  functor IntRa = 
      RegAllocator
	 (structure RaArch = struct

	     structure InsnProps = P
	     structure AsmEmitter = Asm
	     structure I = I
	     structure Liveness=RegLiveness
	     val defUse = P.defUse C.GP
	     val firstPseudoR = 32
	     val maxPseudoR = AlphaCells.maxCell
	     val numRegs = AlphaCells.numCell AlphaCells.GP
	     val regSet = C.getCell C.GP 
	  end)



  (* liveness analysis for floating point registers *)
  structure FregLiveness = 
    Liveness(structure Flowgraph=F
	     structure Instruction=I
	     val defUse = P.defUse C.FP
	     val regSet = C.getCell C.FP 
             val cellset = C.updateCell C.FP)

  (* floating register allocator *)
  functor FloatRa = 
    RegAllocator
       (structure RaArch = struct

          structure InsnProps = P
	  structure AsmEmitter = Asm
	  structure Liveness=FregLiveness
	  structure I = I

	  val defUse = P.defUse C.FP
	  val firstPseudoR = 64
	  val maxPseudoR = AlphaCells.maxCell 
	  val numRegs = AlphaCells.numCell AlphaCells.FP
	  val regSet = C.getCell C.FP 
	end)
end