File: control_hw.h

package info (click to toggle)
mol 0.9.61-6
  • links: PTS
  • area: contrib
  • in suites: woody
  • size: 6,140 kB
  • ctags: 8,491
  • sloc: ansic: 50,560; asm: 2,826; sh: 458; makefile: 373; perl: 165; lex: 135; yacc: 131
file content (133 lines) | stat: -rw-r--r-- 3,725 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
/* 
 *   Creation Date: <1999/03/05 15:38:39 samuel>
 *   Time-stamp: <1999/03/05 15:56:26 samuel>
 *   
 *	<control_hw.h>
 *	
 *	Control hardware (videocontroller in the 7500, 8500)
 *   
 *   Copyright (C) 1999 Samuel Rydh (samuel@ibrium.se)
 *	
 *   Based upon hardware information from the linuxppc kernel:
 *
 *   	Copyright (C) 1998 Daniel Jacobowitz <dan@debian.org>
 *   	Copyright (C) 1996 Paul Mackerras.
 *   	Copyright (C) 1998 Jon Howell
 *    
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation
 *   
 */

#ifndef _H_CONTROL_HW
#define _H_CONTROL_HW

#include <sys/types.h>

/*
 * Structure of the registers for the RADDAC colormap device.
 */
#define DAC_REG_SIZE	0x10
#define DAC_SIZE     	0x40
enum { 
	dacr_addr=0, 
	dacr_d1, 
	dacr_d2, 
	dacr_lut 
};

#define CONTROL_REG_SIZE	0x10
#define CONTROL_SIZE		0x1000	/* this is what OF gives us... */

typedef struct cmap_regs {
        unsigned char 	addr;
        char pad1[15];
        unsigned char 	d1;
        char pad2[15];
        unsigned char 	d2;
        char pad3[15];
        unsigned char 	lut;
        char pad4[15];
} ph_cmap_regs_t;

#if 0
struct preg {                   /* padded register */
        unsigned r;
        char pad[12];
};

struct control_regs {
        struct preg vcount;     /* vertical counter */
        /* Vertical parameters are in units of 1/2 scan line */
        struct preg vswin;      /* between vsblank and vssync */
        struct preg vsblank;    /* vert start blank */
        struct preg veblank;    /* vert end blank (display start) */
        struct preg vewin;      /* between vesync and veblank */
        struct preg vesync;     /* vert end sync */
        struct preg vssync;     /* vert start sync */
        struct preg vperiod;    /* vert period */
        struct preg reg8;
        /* Horizontal params are in units of 2 pixels */
        struct preg hperiod;    /* horiz period - 2 */
        struct preg hsblank;    /* horiz start blank */
        struct preg heblank;    /* horiz end blank */
        struct preg hesync;     /* horiz end sync */
        struct preg hssync;     /* horiz start sync */
        struct preg rege;
        struct preg regf;
        struct preg reg10;
        struct preg reg11;
        struct preg ctrl;       /* display control */
        struct preg start_addr; /* start address: 5 lsbs zero */
        struct preg pitch;      /* addrs diff between scan lines */
        struct preg mon_sense;  /* monitor sense bits */
        struct preg flags;
        struct preg mode;
        struct preg reg18;
        struct preg reg19;
        struct preg res[6];
};
#endif

#define NUM_REGS_CONTROL	32
/* 32 registers */
enum {
	r_vcount=0, 	/* vertical counter */
	/* Vertical parameters are in units of 1/2 scan line */
	r_vswin,	/* between vsblank and vssync */
	r_vsblank,	/* vert start blank */
	r_veblank,	/* vert end blank (display start) */
	r_vewin,	/* between vesync and veblank */
	r_vesync,	/* vert end sync */
	r_vssync,	/* vert start sync */
	r_vperiod,	/* vert period */
	r_reg8,
	/* Horizontal params are in units of 2 pixels */
	r_hperiod,	/* horiz period - 2 */
	r_hsblank,	/* horiz start blank */
	r_heblank,	/* horiz end blank */
	r_hesync,	/* horiz end sync */
	r_hssync,	/* horiz start sync */
	r_rege,
	r_regf,
	r_reg10,
	r_reg11,
	r_ctrl,	 	/* display control */
	r_start_addr,	/* start address: 5 lsbs zero */
	r_pitch,	/* addrs diff between scan lines */
	r_mon_sense,	/* monitor sense bits */
	r_flags,
	r_mode,
	r_reg18,
	r_reg19,
	r_res1,
	r_res2,
	r_res3,
	r_res4,
	r_res5,
	r_res6,
};


#endif /* _H_CONTROL_HW */