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Source: opensta
Section: electronics
Priority: optional
Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Uploaders: Ruben Undheim <ruben.undheim@gmail.com>
Build-Depends: debhelper-compat (= 12),
cmake,
tcl-dev,
swig,
bison,
flex,
libreadline-dev,
zlib1g-dev,
txt2man
Standards-Version: 4.4.1
Vcs-Browser: https://salsa.debian.org/electronics-team/opensta
Vcs-Git: https://salsa.debian.org/electronics-team/opensta.git
Homepage: https://github.com/The-OpenROAD-Project/OpenSTA
Package: opensta
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}
Description: Gate-level Static Timing Analyzer
After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a Tcl interface for entering commands for analysing designs.
.
It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
Package: opensta-dev
Architecture: any
Section: libdevel
Depends: ${misc:Depends}
Description: Gate-level Static Timing Analyzer - development files
After synthesis, place and route of a digital circuit, it is necessary to
verify the timing of the design. OpenSTA is a tool for doing exactly that. It
has a Tcl interface for entering commands for analysing designs.
.
It typically takes as input a verilog netlist, a liberty file, and other
parasitics information from the placed and routed design.
.
This package contains the header files and some libraries for development.
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