File: VerilogLex.ll

package info (click to toggle)
opensta 0~20191111gitc018cb2+dfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: bullseye, sid
  • size: 5,116 kB
  • sloc: cpp: 99,117; tcl: 8,530; yacc: 1,435; lex: 894; makefile: 541; sh: 107
file content (186 lines) | stat: -rw-r--r-- 3,892 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
%{

// OpenSTA, Static Timing Analyzer
// Copyright (c) 2019, Parallax Software, Inc.
// 
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// 
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
// 
// You should have received a copy of the GNU General Public License
// along with this program.  If not, see <https://www.gnu.org/licenses/>.

#include "Machine.hh"
#include "Debug.hh"
#include "VerilogNamespace.hh"
#include "VerilogReaderPvt.hh"
#include "VerilogParse.hh"

#define YY_NO_INPUT

int verilog_line = 1;
static std::string string_buf;

void
verilogFlushBuffer()
{
  YY_FLUSH_BUFFER;
}

%}

/* %option debug */
%option noyywrap
%option nounput
%option never-interactive

%x COMMENT
%x ATTRIBUTE
%x QSTRING

SIGN	"+"|"-"
UNSIGNED_NUMBER [0-9][0-9_]*
BLANK	[ \t\r]
EOL	\r?\n
ID_ESCAPED_TOKEN \\[^ \t\r\n]+[\r\n\t ]
ID_ALPHA_TOKEN [A-Za-z_][A-Za-z0-9_$]*
ID_TOKEN {ID_ESCAPED_TOKEN}|{ID_ALPHA_TOKEN}

%%

^[ \t]*`.*{EOL} { /* Macro definition. */
	sta::verilog_reader->incrLine();
	}

"//"[^\n]*{EOL} { /* Single line comment. */
	sta::verilog_reader->incrLine();
	}

"/*"	{ BEGIN COMMENT; }
<COMMENT>{
.

{EOL}	{ sta::verilog_reader->incrLine(); }

"*/"	{ BEGIN INITIAL; }

<<EOF>> {
	VerilogParse_error("unterminated comment");
	BEGIN(INITIAL);
	yyterminate();
	}
}

"(*"	{ BEGIN ATTRIBUTE; }
<ATTRIBUTE>{
.

{EOL}	{ sta::verilog_reader->incrLine(); }

"*)"	{ BEGIN INITIAL; }

<<EOF>> {
	VerilogParse_error("unterminated attribute");
	BEGIN(INITIAL);
	yyterminate();
	}
}

{SIGN}?{UNSIGNED_NUMBER}?"'"[bB][01_xz]+ {
  VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
  return CONSTANT;
}

{SIGN}?{UNSIGNED_NUMBER}?"'"[oO][0-7_xz]+ {
  VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
  return CONSTANT;
}

{SIGN}?{UNSIGNED_NUMBER}?"'"[dD][0-9_]+ {
  VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
  return CONSTANT;
}

{SIGN}?{UNSIGNED_NUMBER}?"'"[hH][0-9a-fA-F_xz]+ {
  VerilogParse_lval.constant = sta::stringCopy(VerilogLex_text);
  return CONSTANT;
}

{SIGN}?[0-9]+ {
  VerilogParse_lval.ival = atol(VerilogLex_text);
  return INT;
}

":"|"."|"{"|"}"|"["|"]"|","|"*"|";"|"="|"-"|"+"|"|"|"("|")" {
  return ((int) VerilogLex_text[0]);
}

assign { return ASSIGN; }
endmodule { return ENDMODULE; }
inout { return INOUT; }
input { return INPUT; }
module { return MODULE; }
output { return OUTPUT; }
parameter { return PARAMETER; }
defparam { return DEFPARAM; }
reg { return REG; }
supply0 { return SUPPLY0; }
supply1 { return SUPPLY1; }
tri { return TRI; }
wand { return WAND; }
wire { return WIRE; }
wor { return WOR; }

{ID_TOKEN}("."{ID_TOKEN})* {
	VerilogParse_lval.string = sta::stringCopy(sta::verilogToSta(VerilogLex_text));
	return ID;
}

{EOL}	{ sta::verilog_reader->incrLine(); }

{BLANK}	{ /* ignore blanks */ }

\"	{
	string_buf.erase();
	BEGIN(QSTRING);
	}

<QSTRING>\" {
	BEGIN(INITIAL);
	VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
	return STRING;
	}

<QSTRING>{EOL} {
	VerilogParse_error("unterminated string constant");
	BEGIN(INITIAL);
	VerilogParse_lval.string = sta::stringCopy(string_buf.c_str());
	return STRING;
	}

<QSTRING>\\{EOL} {
	/* Line continuation. */
	sta::verilog_reader->incrLine();
	}

<QSTRING>[^\r\n\"]+ {
	/* Anything return or double quote */
	string_buf += VerilogLex_text;
	}

<QSTRING><<EOF>> {
	VerilogParse_error("unterminated string constant");
	BEGIN(INITIAL);
	yyterminate();
	}

	/* Send out of bound characters to parser. */
.	{ return (int) VerilogLex_text[0]; }

%%