1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304
|
/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2014-2019, Linaro Limited
*/
#ifndef __IO_H
#define __IO_H
#include <compiler.h>
#include <kernel/delay.h>
#include <kernel/delay_arch.h>
#include <stdint.h>
#include <types_ext.h>
#include <utee_defines.h>
/*
* Make sure that compiler reads/writes given variable only once. This is needed
* in cases when we have normal shared memory, and this memory can be changed
* at any moment. Compiler does not knows about this, so it can optimize memory
* access in any way, including repeated accesses from the same address.
* These macro enforce compiler to access memory only once.
*/
#define READ_ONCE(p) __compiler_atomic_load(&(p))
#define WRITE_ONCE(p, v) __compiler_atomic_store(&(p), (v))
static inline void io_write8(vaddr_t addr, uint8_t val)
{
*(volatile uint8_t *)addr = val;
}
static inline void io_write16(vaddr_t addr, uint16_t val)
{
*(volatile uint16_t *)addr = val;
}
static inline void io_write32(vaddr_t addr, uint32_t val)
{
*(volatile uint32_t *)addr = val;
}
static inline void io_write64(vaddr_t addr, uint64_t val)
{
*(volatile uint64_t *)addr = val;
}
static inline uint8_t io_read8(vaddr_t addr)
{
return *(volatile uint8_t *)addr;
}
static inline uint16_t io_read16(vaddr_t addr)
{
return *(volatile uint16_t *)addr;
}
static inline uint32_t io_read32(vaddr_t addr)
{
return *(volatile uint32_t *)addr;
}
static inline uint64_t io_read64(vaddr_t addr)
{
return *(volatile uint64_t *)addr;
}
static inline void io_mask8(vaddr_t addr, uint8_t val, uint8_t mask)
{
io_write8(addr, (io_read8(addr) & ~mask) | (val & mask));
}
static inline void io_mask16(vaddr_t addr, uint16_t val, uint16_t mask)
{
io_write16(addr, (io_read16(addr) & ~mask) | (val & mask));
}
static inline void io_mask32(vaddr_t addr, uint32_t val, uint32_t mask)
{
io_write32(addr, (io_read32(addr) & ~mask) | (val & mask));
}
static inline uint64_t get_be64(const void *p)
{
return TEE_U64_FROM_BIG_ENDIAN(*(const uint64_t *)p);
}
static inline void put_be64(void *p, uint64_t val)
{
*(uint64_t *)p = TEE_U64_TO_BIG_ENDIAN(val);
}
static inline uint32_t get_be32(const void *p)
{
return TEE_U32_FROM_BIG_ENDIAN(*(const uint32_t *)p);
}
static inline void put_be32(void *p, uint32_t val)
{
*(uint32_t *)p = TEE_U32_TO_BIG_ENDIAN(val);
}
static inline uint16_t get_be16(const void *p)
{
return TEE_U16_FROM_BIG_ENDIAN(*(const uint16_t *)p);
}
static inline void put_be16(void *p, uint16_t val)
{
*(uint16_t *)p = TEE_U16_TO_BIG_ENDIAN(val);
}
static inline void put_le32(const void *p, uint32_t val)
{
*(uint32_t *)p = val;
}
static inline uint32_t get_le32(const void *p)
{
return *(const uint32_t *)p;
}
static inline void put_le64(const void *p, uint64_t val)
{
*(uint64_t *)p = val;
}
static inline uint64_t get_le64(const void *p)
{
return *(const uint64_t *)p;
}
/* Unaligned accesses */
struct __unaligned_u16_t { uint16_t x; } __packed;
struct __unaligned_u32_t { uint32_t x; } __packed;
struct __unaligned_u64_t { uint64_t x; } __packed;
static inline uint64_t get_unaligned_be64(const void *p)
{
const struct __unaligned_u64_t *tmp = p;
return TEE_U64_FROM_BIG_ENDIAN(tmp->x);
}
static inline void put_unaligned_be64(void *p, uint64_t val)
{
struct __unaligned_u64_t *tmp = p;
tmp->x = TEE_U64_TO_BIG_ENDIAN(val);
}
static inline uint32_t get_unaligned_be32(const void *p)
{
const struct __unaligned_u32_t *tmp = p;
return TEE_U32_FROM_BIG_ENDIAN(tmp->x);
}
static inline void put_unaligned_be32(void *p, uint32_t val)
{
struct __unaligned_u32_t *tmp = p;
tmp->x = TEE_U32_TO_BIG_ENDIAN(val);
}
static inline uint16_t get_unaligned_be16(const void *p)
{
const struct __unaligned_u16_t *tmp = p;
return TEE_U16_FROM_BIG_ENDIAN(tmp->x);
}
static inline void put_unaligned_be16(void *p, uint16_t val)
{
struct __unaligned_u16_t *tmp = p;
tmp->x = TEE_U16_TO_BIG_ENDIAN(val);
}
static inline void put_unaligned_le64(void *p, uint64_t val)
{
struct __unaligned_u64_t *tmp = p;
tmp->x = val;
}
static inline uint64_t get_unaligned_le64(const void *p)
{
const struct __unaligned_u64_t *tmp = p;
return tmp->x;
}
static inline void put_unaligned_le32(void *p, uint32_t val)
{
struct __unaligned_u32_t *tmp = p;
tmp->x = val;
}
static inline uint32_t get_unaligned_le32(const void *p)
{
const struct __unaligned_u32_t *tmp = p;
return tmp->x;
}
static inline void put_unaligned_le16(void *p, uint16_t val)
{
struct __unaligned_u16_t *tmp = p;
tmp->x = val;
}
static inline uint16_t get_unaligned_le16(const void *p)
{
const struct __unaligned_u16_t *tmp = p;
return tmp->x;
}
/*
* Set and clear bits helpers.
*
* @addr is the address of the memory cell accessed
* @set_mask represents the bit mask of the bit(s) to set, aka set to 1
* @clear_mask represents the bit mask of the bit(s) to clear, aka reset to 0
*
* io_clrsetbits32() clears then sets the target bits in this order. If a bit
* position is defined by both @set_mask and @clear_mask, the bit will be set.
*/
static inline void io_setbits32(vaddr_t addr, uint32_t set_mask)
{
io_write32(addr, io_read32(addr) | set_mask);
}
static inline void io_clrbits32(vaddr_t addr, uint32_t clear_mask)
{
io_write32(addr, io_read32(addr) & ~clear_mask);
}
static inline void io_clrsetbits32(vaddr_t addr, uint32_t clear_mask,
uint32_t set_mask)
{
io_write32(addr, (io_read32(addr) & ~clear_mask) | set_mask);
}
static inline void io_setbits16(vaddr_t addr, uint16_t set_mask)
{
io_write16(addr, io_read16(addr) | set_mask);
}
static inline void io_clrbits16(vaddr_t addr, uint16_t clear_mask)
{
io_write16(addr, io_read16(addr) & ~clear_mask);
}
static inline void io_clrsetbits16(vaddr_t addr, uint16_t clear_mask,
uint16_t set_mask)
{
io_write16(addr, (io_read16(addr) & ~clear_mask) | set_mask);
}
static inline void io_setbits8(vaddr_t addr, uint8_t set_mask)
{
io_write8(addr, io_read8(addr) | set_mask);
}
static inline void io_clrbits8(vaddr_t addr, uint8_t clear_mask)
{
io_write8(addr, io_read8(addr) & ~clear_mask);
}
static inline void io_clrsetbits8(vaddr_t addr, uint8_t clear_mask,
uint8_t set_mask)
{
io_write8(addr, (io_read8(addr) & ~clear_mask) | set_mask);
}
/*
* Poll on a IO memory content or timeout
*
* @_addr is the address of the memory cell accessed
* @_val represents the val of the memory cell accessed
* @_cond represents the condition to get the correct value
* @_delay_us represents the read interval in mircorseconds
* @_timeout_us represents the timeout period in microseconds
*
* @return nonzero value means timeout, 0 means got right value
*/
#define IO_READ32_POLL_TIMEOUT(_addr, _val, _cond, _delay_us, _timeout_us) \
({ \
uint64_t __timeout = timeout_init_us(_timeout_us); \
uint32_t __delay = (_delay_us); \
\
while (!timeout_elapsed(__timeout)) { \
(_val) = io_read32(_addr); \
if (_cond) \
break; \
udelay(__delay); \
} \
(_val) = io_read32(_addr); \
!(_cond); \
})
#endif /*__IO_H*/
|