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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<head>
<title> pcb-rnd user manual </title>
<meta http-equiv="Content-Type" content="text/html;charset=us-ascii">
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<body>
<h1 nopdf="yes"> pcb-rnd - user manual </h1>
<h2> 2. Model of the world </h2>
<p>
Pcb-rnd is designed to handle the geometric data of a PCB. This section describes
how pcb-rnd represents reality (e.g. copper shapes) in memory.
<h3> 2.1. Board </h3>
<p>
Each design pcb-rnd handles is a <i>board</i>. The board has global properties and hosts
layers. Most drawing primitives (objects) are on layers. This section describes
the most important global properties.
<p>
Raw <b>board size</b> is given as a width and a height. This is the size
of the preferred drawing area on screen, but for rectangular boards this
can be the real board size. More often final board dimensions are
specified by drawing objects drawn on boundary layer groups within this
area. If the board is not rectangular, the contour must be specified on
boundary layers and the board size must be large enough that the outline
fits in it.
<p>
<b>Netlist</b> is the list of logical connections to be realized in copper.
A netlist is a list of named <i>nets</i>. Each net consists of a list of
<i>terminals</i> (pins or pads) to connect. A terminal is given as
refdes-pinname, e.g. U4-7 means "pin number 7 in subcircuit called U4".
<p>
<b>Fonts</b> are normally embedded in the design file in order to guarantee
that the file can be ported and will look the same on different hosts.
<p>
Configuration: misc editor settings, such as grid size and offset, plugin
settings.
<p>
Route styles.
<h3> 2.2. Layers </h3>
<p>
The main use of pcb-rnd is to aide the user in the process of producing real
pcbs composed of real <i>physical layers</i>. pcb-rnd also refers to layers to
conceptualize this process, but pcb-rnd layers are different than the
<i>physical layers</i>.
<p>
Unlike a <i>physical layer</i>, a pcb-rnd layer has no thickness. Any pcb-rnd
layer is always part of a <i>layer group</i>. It is a 2 dimensional logical
canvas, similar to layers in image manipulation software like GIMP. In pcb-rnd
there are <i>explicit</i>, <i>virtual</i> or <i>implicit</i> layers. An
explicit layer contains drawing primitives (<a href="#objects">objects</a>)
placed by the user. The user has full control over an explicit layer: objects
can be added or removed or changed any time. A virtual or implicit layer has no
such flexibility: pcb-rnd computes its content from explicit layers and there's
no way for the user to change the result directly.
<p>
Pcb-rnd currently maintains some layers types as virtual layers for
compatibility with the PCB package. In a pcb-rnd board design started from
default configuration options, the mask, silk, and paste layers currently start
out as virtual layers. The content for these layers is computed by pcb-rnd as
for a virtual or explicit layer, until the user decides to use features that
require user control over one or more of the layers in the group. At that
point, the virtual layer is replaced with an explicit layer group.
<p>
For example, in pcb-rnd when using one of the gtk GUIs, if the user right
clicks on a solder mask ('mask') layer and choose an option to 'insert new
layer before this one', pcb-rnd replaces the virtual mask layer with an explicit
mask layer group. The mask layer group can contain one to many pcb-rnd layers
each with individual settings to control implicit generation, and additive or
subtractive behavior when adding objects to the layers.
<p>
In CLI (e.g. action arguments), layers are referenced using
<a href="../09_appendix/layer_addr.html">layer addressing.</a>
<h3> 2.3. Layer Groups </h3>
<p>
One or more explicit layers form a <i>layer group</i>. All pcb-rnd layers
of a layer group will end up on the same physical layer. The visibility of
layers in a layer group are toggled together. Having more than one layer
in a group may be useful to:
<ul>
<li> exploit that layers have different
<a href="../09_appendix/layer_colors.html">drawing color on screen:</a>
e.g. there can be a signal and a gnd layers with different color in
the same layer group, on the same physical layer.
<li> on composite-groups (mask, paste, silk), layers are combined using
their properties: some layers may draw, others may clear; some layers
may contain auto-generated objects. The order of layers does matter
in draw-clear combinations.
</ul>
<p>
Since <i>layer groups</i> donate the physical layers, a board stack-up
is built of layer groups. Substrates are layer groups without drawable
layers in them. The mask, paste, silk layer groups behave the same and
can host zero or more logical layers.
<p>
Each layer group has a main type. Main types are:
<ul>
<li> <b>copper</b> for signal layers
<li> <b>silk</b> for silkscreen layers
<li> <b>mask</b> for solder masks
<li> <b>paste</b> for solder paste
<li> <b>boundary</b> for the contour of the board
<li> <b>mech</b> mechanical information (e.g. cutouts, slots, adhesive; sent to the board fab)
<li> <b>doc</b> documentation and metadata (not sent to the board fab)
</ul>
<p>
Each layer group has a location. Locations are:
<ul>
<li><b>top</b> (used to be the "component side" in the age of thru-hole components)
<li><b>bottom</b> (used to be the "solder side" in the age of thru-hole components)
<li><b>intern</b> (sandwiched between other layers)
<li><b>global</b> (affects all physical layers, thus has no specific location)
</ul>
<p>
Not all combination of type and location are supported: e.g. for a boundary
layer group the location is always global. The table below lists whether a
combination is supported or not.
<p>
<table border=1>
<caption><b>Layer Combination Support</b>
<tr><th> <th> top <th> bottom <th> intern <th> global <th> composite
<tr><th> copper <td> yes <td> yes <td> yes <td> no <td> no
<tr><th> silk <td> yes <td> yes <td> no <td> no <td> yes
<tr><th> mask <td> yes <td> yes <td> no <td> no <td> yes
<tr><th> paste <td> yes <td> yes <td> no <td> no <td> yes
<tr><th> boundary <td> no <td> no <td> no <td> yes <td> no
<tr><th> mech <td> yes <td> yes <td> yes <td> yes <td> maybe
<tr><th> doc <td> yes <td> yes <td> yes <td> yes <td> maybe
</table>
<p>
Note: for some layer types whether compositing is allowed depends on the
subtype (purpose).
<p>
Each layer group has a <i>purpose</i> field, which functions as a
subtype. The value is a free form text for user defined groups, but pcb-rnd
recognizes (and handles specially) the following combinations:
<p>
<table border=1>
<caption><b>Layer purpose combinations recongized </b>
<tr><th> main type <th> purpose <th> special meaning
<tr><td> boundary <td> uroute <td> unplated, routed bounary: routed outline of the board
<tr><td> boundary <td> proute <td> plated, routed bounary: routed outline of the board with copper plating
<tr><td> mech <td> uroute <td> unplated, routed inner cutout: unplated slots and small inner cutouts, done with drilling or routing or punch-through
<tr><td> mech <td> proute <td> plated, routed inner cutout: plated slots and small inner cutouts, done with drilling or routing or punch-through (typical for oval/rectanglar pins)
</table>
<p>
The following combinations are conventions many footprints and boards
would follow:
<p>
<table border=1>
<caption><b>Layer purpose combinations recommended </b>
<tr><th> main type <th> purpose <th> location <th> special meaning
<tr><td> boundary <td> cut <td> (global) <td> unplated, straight line cuts at board outline
<tr><td> boundary <td> vcut <td> (global) <td> unplated, straight line v-cuts (or grooves) at board outline
<tr><td> doc <td> assy <td> top or bottom <td> assembly drawing (for populating the board)
<tr><td> doc <td> fab <td> top <td> fab instructions (for board fabrication: cuts and drills)
<tr><td> doc <td> ko.courtyard <td> top or bottom <td> keepout: component body above (or below) the board surface (polygons)
<tr><td> doc <td> ko@<i>lt</i> <td> respectively <td> keepout: nothing shall be drawn on layer type <i>lt</i> that intersects objects on this layer; <i>lt</i> is <i>location-type</i>, e.g. top-copper, bottom-silk, etc.
<tr><td> doc <td> placement <td> any <td> placement helpers, e.g. where board edge should be relative to a connector
<tr><td> mech <td> adhesive <td> top or bottom <td> adhesive (glue) pattern printed on the board to keep parts in place during reflow
<tr><td> mech <td> finish.gold <td> top or bottom <td> gold finish (typical for copper fingers intended for slots/connectors/contacts)
<tr><td> mech <td> finish.carbon<td> top or bottom <td> carbon finish (typical for under rubber push buttons)
</table>
<p>
Layer group attributes interpreted by pcb-rnd core:
<p id="layer_group_attr">
<table border=1>
<caption><b>Layer group attributes</b>
<tr><th> layer group attribute name <th> description
<tr><td> thickness <td> thickness of the physical layer, given with unit (e.g. 0.2mm or 200um or 50mil)
<tr><td> <i>plugin</i>::thickness <td> overrides the above thickness value for a specific plugin, if the plugin supports it; for example openems::thickness will use a different layer group thickness for the given layer group when exporting to openems
<tr><td> dielectric <td> Relative dielectric constant, typically for substrate layer groups, Er (unitless)
</table>
<p>
In CLI (e.g. action arguments), layers groups are referenced using
<a href="../09_appendix/layer_addr.html">layer group addressing.</a>
<h3 id="objects"> 2.4. Basic Drawing Objects </h3>
<p>
Pcb-rnd supports a small number of basic drawing objects, from which complex
objects can be build. The following figure demonstrates all basic objects:
<p>
<img src="objects_basic.png" alt="[Arc, Line, Polygon, Pin, Via]">
<p>
Objects have flags that control their behavior. The following flags are common
to all objects:
<p>
<table>
<caption><b>Object Flags</b>
<tr><th>name <th> description
<tr><td>selected <td> selected by the user ("cyan")
<tr><td>found <td> found as a galvanic connection in the last connection lookup ("green")
<tr><td>warn <td> offending object e.g. in a short circuit ("orange")
<tr><td>lock <td> locked by the user: can't be selected, moved or changed using the basic mouse/keyboard actions (still can be copied, selected by query() and edited by propedit())
</table>
<h4> 2.4.1. Line Objects </h4>
<p>
Lines are round ended straight line segments with a width and
a clearance. The above image shows 3 lines connected. Lines are mainly
used to construct traces. A line is always on a specific layer. The user
interface allows drawing lines aligned to 90 or 45 degree axes or
lines with random angle.
<p>
A line is specified by its two endpoints, width and clearance:
<p>
<img src="obj_line.png" alt="[Line interacting with a polygon]" height="200">
<p>
A <i>clearance</i> is the gap between a line and the surrounding polygon
in the same layer group. The gap is made only if the surrounding polygon has
the "clearpoly" flag set and the line has the "clearline" flag set. If either
of these flags is not set, no gap is made - or in pcb-rnd terminology,
the line is joined to the polygon.
<p>
<table>
<caption><b>Line Object Flags</b>
<tr><th>name <th> description
<tr><td>clearline <td> clears polygons with the "clearpoly" flag in the same layer group
</table>
<h4> 2.4.2. Arc Objects </h4>
<p>
Arcs are round ended circular arcs with trace width and clearance. They
behave like lines in all respects.
<p>
<img src="obj_arc.png" alt="[Arc interacting with a polygon]" height="200">
<p>
Although the arc is described with its center, radius, start and end
angles, the user interface may offer drawing arcs by endpoints.
<p>
<table>
<caption><b>Arc Object Flags</b>
<tr><th>name <th> description
<tr><td>clearline <td> clears polygons with the "clearpoly" flag in the same layer group
</table>
<h4> 2.4.3. Polygon Objects </h4>
<p>
Polygons are solid, filled copper areas with optional holes in them. Polygon
contour consists of lines - when they look curvy, its really high resolution
line approximation. There are two type of holes in a polygon: <i>explicit</i>,
user drawn holes and <i>clearance</i> cutouts. User drawn holes are "negative"
polygons drawn manually. To keep polygons simple, if an user drawn hole
touches the contour of a polygon, the hole is removed and the contour is
modified; if two holes touch, they are merged into one hole.
<p>
If the polygon has the "clearpoly" flag set (default), clearance cutouts are
automatically inserted around objects on the same layer group:
<ul>
<li> lines and arcs, if they have the "clearline" flag set (default)
<li> padstacks, if they are not connected to the polygon by thermals
</ul>
<p>
Overlapping or touching polygons are not automatically merged. An object
with the "clearline" flag set will clear all "clearpolys" it is over -
if there are multiple such polygons overlapping under the objects (on
the same layer group), all such polygons get the clearance cutout.
<p>
If a polygon has the "clearpolypoly" flag set, it clears any other polygon
that does <b>not</b> have the "clearpolypoly" flag set but has the
"clearpoly" set. In other words, a "clearpolypoly" polygon behaves the same
as a line/arc that has the "clearline" flag.
<p>
If a polygon is cut into multiple islands, the behavior depends on the
"fullpoly" flag of the polygon. If it is not set (default), only the largest
island is kept, else all islands are kept. In the "fullpoly" mode islands
will have no galvanic connection (unless the user adds vias and connect them
on another layer), still the program will handle all islands as a single
polygon. This is risky: the program will indicate connection between polygon
islands that are not really connected, only because they are part of the same
polygon!
<p>
Any polygon may have its <i>enforce_clearance</i> set to non-zero, in which
case any object that has a clearance within the given polygon by flags will
make a clearance at least as large as the polygon's <i>enforce_clearance</i>
(but larger, if the object requested larger clearance than
the polygon's <i>enforce_clearance</i>). Note: this applies only if
the object has the clearline flag and the polygon has the clearpoly flag.
<p>
<table border=1>
<caption><b>Polygon Object Flags</b>
<tr><th>name <th> description
<tr><td>clearpoly <td> should have clearance around objects, if the objects have the appropriate flags too
<tr><td>fullpoly <td> keep all islands, not only the largest
</table>
<h4> 2.4.4. Text Objects </h4>
<p>
A text object is string and a series of symbols (pcb-rnd's terminology for
glyph). Symbols are built of lines and are stored in the font. Each board
can have its own font, but there can be only one font per board. When
the string of the text is edited, the object is rendered again so that the
new string appears.
<p>
Text objects can be placed on copper and silk layers.
Each text object has a scale_x, a scale_y and a scale parameter that
determine its size. If scale_x is non-zero, it is the width
multiplier on the neutral font width; if scale_y is non-zero, it
is the height multiplier on the normal font height. When any of the
two is zero, it is replaced by scale/100.
<p>
Thus scale_x=1 and scale_y=1 means symbols are rendered in 1:1 size.
Alternatively scale_x=0 and scale_y=0 and scale=100 means the same.
<p>
Text has a thickness field; if it is non-zero,
it specifies the stroke (line and arc) thickness of symbols (glyphs); if it
is zero, the thickness value is calculated from scale.
<p>
By default, the clearance around text is rendered as a round corner
rectangular cutout. If the tight_clearance attribute on the text object
is specified and the value is "yes" or "true" or "1", a more accurate
clearance is calculated that follows the true shape of the text object. If
the clearance field of the text object is not 0, it determines the
clearance (gap) to polygon in thight_clearance mode (if the clearance happens,
see flags, and the value not overridden from the polygon side).
<p>
The Y coordinates of a text object are mirrored if the ONSOLDER flag is set
(which means the text is mirrored over the X axis). The X coordinates of a
text object are mirrored if the mirror_x attribute is true (which means the
text is mirrored over the Y axis). NOTE: the point of placement (which
corner is placed at the specified X;Y coordinate) depends on mirroring.
<p>
Bug: copper text can not participate in short circuits, the galvanic connection
checker code skips texts.
<h4> 2.4.5. Subcircuits </h4>
<p id="subcircuit">
A subc (subcircuit) is a group of objects with its own, local layer
information. All layers of a subc are <i>bound</i> layers, that is, the user
is free to choose on which actual board layer it is placed on.
There is no limitation on what layers or objects a subc can contain.
<p id="subc">
The main uses of subc are:
<ul>
<li> footprint
<li> copy&paste anonymous repetitive section of a circuit
</ul>
<h5 id="footprints"> 2.4.5.1 Subcircuits as footprints </h5>
<p>
A subcircuit may be an instance (copy) of a footprint. The subcircuit is
placed on the board or loaded into a paste buffer (the footprint lives in
the footprint library).
<p>
In the footprint form the construct is small and flexible. It describes
all the physical parts, like pins, pads, silk lines. In the same time a
footprint leaves many details blank, e.g. it doesn't specify exact layers,
it doesn't have font and the refdes is random.
<p>
When the footprint is loaded, it becomes a subcircuit. The subcircuit inherits all
the physical properties and the blank details are filled in with the data taken
from the current board: the layer binding is done, all parts of the subcircuit
lands on a specific board layer; the refdes is rendered using the font in
the current board.
<p>
The footprint -> subcircuit instantiation is also a copy. Once the subcircuit
is created from a footprint, the subcircuit is a self-containing object and
does not have any direct reference to the footprint it was once derived from.
Changes to the original footprint will <b>not</b> affect the subcircuits.
<p>
In other words, a footprint is an abstract recipe, part of a
library, while a subcircuit is a land pattern already embedded in a
specific design and describes actual copper and silk.
<p>
Currently a subcircuit or footprint can contain any object on any layer
that a board can contain.
<p>
Commonly used subcircuit attributes:
<p>
<table border=1>
<caption><b>Subcircuit attributes</b>
<tr><th> subcircuit attribute name <th> description
<tr><td> refdes <td> unique identifier, e.g. "C42" - pcb-rnd code will use this when present
<tr><td> value <td> informal value, e.g. "15 pF"
<tr><td> footprint <td> informal footprint description, e.g. "1206"
</table>
<p>
When a subcircuit is a footprint, it normally has the <i>refdes</i> attribute set.
Refdes is the name that identifies the part on the netlist. Some objects
of a footprint will have the <i>term</i> attribute to turn those object into
terminals (representing pins or pads). If multiple objects have the same
<i>term</i> attribute value, they are all contributing to the same terminal.
<p>
When the terminal object is a single <a
href="#padstack"><i>padstack</i></a>, it is called a <a href="#lightterm">
<i>light terminal</i></a>. When the terminal is built using multiple objects,
it is called a <i>heavy terminal</i>.
<p>
A connection on the netlist is identified as <i>refdes</i>-<i>term</i>, e.g.
U5-3 means "the object(s) whose term attribute is 3 within the subcircuit
whose refdes attribute is 'U5'".
<p>
If its <i>nonetlist</i> flag is set, the subcircuit is not intended to be
part of the netlist; that is, it will not cause shorts and will not be
removed on a forward annotation (schematics/netlist import).
<h5> 2.4.5.2 Subcircuits as repetitive modules </h5>
<p>
If the repetitive module is specified as a refdes-named device on
the schematics, it is really just a footprint. Else it is a non-footprint
subcircuit.
<p>
Compared to subcircuits as footprint, a non-footprint subcircuit will not have
a refdes attribute and will not have terminals. It will also have the
nonetlist flag set.
<h5> 2.4.5.3 Subcircuit aux layer </h5>
<p>
A subcircuit needs to have an <i>aux layer</i>. The name of this layer
is <i>subc-aux</i>, with type VIRTUAL and MISC, and is on top, bottom or intern.
It hosts three objects placed when the subc was first created:
<ul>
<li> a zero length line at the <i>origin</i> of the subc, with attribute <i>subc-role=origin</i>
<li> an 1mm long horizontal line in the positive x direction from the <i>origin</i>, with attribute <i>subc-role=x</i>
<li> an 1mm long vertical line in the positive y direction from the <i>origin</i>, with attribute <i>subc-role=y</i>
</ul>
<p>
These objects specify the neutral state of the subcircuit. If the subcircuit
goes through any transformation (rotation, translation/move, mirroring, etc.),
these objects are also transformed (just like any other object in the subc).
Looking at the current state of these objects and the location flag of the
aux layer, the code can work out the net result of all transformations the
subc suffered since creation.
<h5> 2.4.5.4 Subcircuit uid </h5>
<p>
Each subcircuit has a globally unique ID generated (using libminuid) when the
subcircuit is first created from scratch. The uid field is retained through
copies as it is used to identify the original source of a footprint even
if the footprint had minor modifications. The user shall change the uid if
a substantial modification is made to a footprint.
<h4 id="padstack"> 2.4.6. Pad stacks </h4>
<p>
A pad stack is a generic pin/pad/via object that may contain any combination
of:
<ul>
<li> a hole (plated or unplated, thru-hole or blind/buried)
<li> a pad shape that can be different on each layer group type
<li> thermal relief info on a per layer basis
</ul>
<p id="lightterm">
Pad stacks are flexible enough to cover the majority of the simple pin/pad/via
cases. In a subcircuit, marked as a terminal, a pad stack is called a
<i>light terminal</i>. This concept exist in parallel to the <i>heavy terminal</i>
concept: a heavy terminal consists of multiple objects (e.g. polygons, lines,
arcs, pad stacks), all tagged to the same terminal. When the pad stack model
is not capable to describe a complicated pin or pad, the user should chose the
heavy terminal model. A typical example is the center pad of a QFN footprint
with vias for heat transfer and a specific pattern of paste. The strength
of a pad stack is it's relative simplicity and that all objects on the vertical
stack are bundled together; the strength of the heavy model is its flexibility:
anything that can be drawn on board can be turned into a heavy terminal.
<p>
The optional hole of the pad stack is useful if the pad stack is to be used
as a mounting hole, via or pin. The span of the hole is described by two
integers: how far the hole starts and ends from the top or bottom copper
layer group, counted in copper layer groups.
<p>
A simple all-way-thru hole's span is 0;0, which means it starts at the
top copper group and ends on the bottom copper group. Or precisely,
"starts 0 groups down from top copper group and spans until 0 groups up
from the bottom group". That is, when hol span values are positive,
the top of the hole is counted from the top copper group down and the
bottom of the hole is counted from the bottom group up. If a span value
is negative, it is counted from the other side, e.g. a 0;-3 means:
"hole top is 0 groups down from top copper group, hole bottom is <i>3 groups
down from the top copper group</i>". Or in other words, the topmost four copper
layer groups are connected by the via.
<p>
The plating of the hole is a boolean and is independent of any
other parameter.
<p>
For each layer group type, the user may specify zero or one pad shape.
<table border=1>
<caption><b>Pad stack layer group types</b>
<tr><th>name <th> remarks
<tr><td>top silk <td>
<tr><td>top paste <td>
<tr><td>top mask <td> the first negative layer is used
<tr><td>top copper <td>
<tr><td>intern copper <td> the same pad will be used on all internal copper groups
<tr><td>bottom copper <td>
<tr><td>bottom mask <td> the first negative layer is used
<tr><td>bottom paste <td>
<tr><td>bottom silk <td>
</table>
<p>
<table border=1>
<caption><b>Pad shapes</b>
<tr><th>name <th> description
<tr><td>fillcircle <td> x;y offset of the center, diameter
<tr><td>line <td> round or square cap, from x1;y1 to x2;y2 with the specified thickness
<tr><td>simple-polygon <td> a simple polygon has a single outer contour and no holes
<tr><td>hshadow <td> n/a
</table>
<p>
Pad shape hshadow is a special construct: when drawing a clearance around
the shape, it pretends to be a copy of the hole or slot shape, but it never
has any visible (positive) effect on the target layer. Typical use is inner
layer clearance around a via that should not have a copper ring on that layer.
<p>
The pad stack has an origin, a 0;0 point where it is grabbed. If the pad stack
features a hole, the origin is the center point of the hole. Pad shapes are
all defined in a way that they do not have to be concentric with the hole or
the origin. This allows asymmetric pads.
<p>
In case of blind/buried vias, the internal copper layer pads are applied
only on layers with hole span. However, this does <b>not</b> apply to top/bottom
shapes, those are always explicit. This means it is possible to use a pad stack
as a pad-pair of an board edge connector, having a copper pad on the top
layer and one on the bottom layer, even without having a (plated) hole in between.
The code will assume connection between the pads only if the pad stack has a
plated hole.
<p>
If the <i>global clearance</i> is set, it overrides the per layer type
clearance and the padstack will have the same global clearance on all
layer groups on which it has copper objects.
<p>
<table border=1>
<caption><b>Typical pad stack examples</b>
<tr><th>name <th> description
<tr><td>rectangular smd pad <td> no hole; square cap line or polygon on top copper, top mask and top paste
<tr><td>simple pin or via <td> plated hole and the same filled circle on all copper layers; if pin, a slightly bigger circle on the mask layers
<tr><td>octagon pin or via <td> plated hole and the same simple polygon (octagon shaped) on all copper layers; if pin, a slightly bigger polygon on the mask layers
<tr><td>'oblong' pin <td> plated hole, a short round cap line segment on the bottom copper and mask layers, filled circle on all other copper layers and on the top mask layer
<tr><td>blind via <td> plated hole and the same filled circle on internal and top copper layers - nothing on the bottom copper layer
<tr><td>power jack with slot <td> n/a - can not be done with pad stack as the plated slots for the pins can not be represented as plated round holes - use heavy terminals instead
</table>
<p>
Pad stack <i>prototypes</i> (templates) are stored only once per pcb_data_t (only once per
board for vias or per each subcircuit for terminals). The actual pad stacks
placed on the board (or in subcircuit) are called <i>pad stack references</i>.
A pad stack reference has its own x;y coordinate (within the board or
subcircuit), a rotation angle and a mirror flag. This means if a TQFP chip
has 48 pads along 4 sides, in the simplest setup there will be onlt one pad
stack prototype and 48 pad stack references using the same prototype with
different coordinates and rotations.
<p>
Each padstack reference has an optional <i>global clearance</i>; if it is
non-zero, this value is used as clearance on all layers for this instance.
When it is zero, the prototype's per shape clearance applies, which makes it
possible to have different clearance for internal layers, for example.
<p>
Each padstack reference has a per board layer list of thermal relief types.
<p>
A thermal relief property is added to the copper rings of a via when it is
connected to the surrounding polygon of any individual layer. Physical designs
may use thermal reliefs to enable easy hand soldering, or reduce occurrence of
tombstoning in automated production.
<p>
The following thermal relief options are available:
<table border=1>
<caption><b>Pad/Pin/Via Thermal Relief</b>
<tr><th>Thermal Relief <th> Appearance <td width=20%> <th>Thermal Relief <th> Appearance
<tr><td>no connection<td> <img src="via_therm_noconn.png" alt="unconnected via">
<td><td>solid <td> <img src="via_therm_solid.png" alt="solid thermal">
<tr><td>round x 90 <td> <img src="via_therm_round_x90.png" alt="Thermal relief arc style">
<td><td>round x 45 <td> <img src="via_therm_round_x45.png" alt="Thermal relief arc style, 45deg">
<tr><td>crossbar x 90<td> <img src="via_therm_sharp_x90.png" alt="Thermal relief crossbar style, 90deg">
<td><td>crossbar x 45<td> <img src="via_therm_sharp_x45.png" alt="Thermal relief crossbar style, 45deg">
</table>
<h4> 2.4.7. Rat line Objects </h4>
<p>
A rat line represents a logical connection that is not yet realized in copper.
It requires a loaded netlist for generation, and relies on calculations for any
existing copper layers that connect terminals on the pcb-rnd board. Rat
connections are straight line connections between the terminals of any two
drawing primitives that aren't yet connected
<h4> 2.4.8 Gfx objects </h4>
<p>
A gfx object is a layer object that hosts a rectangular custom graphics -
typically pixel graphics. The raw graphics is rectangular ans has its own
size (width and height), which is scaled to the rectangular size of the gfx
object, the rotated and/or mirrored as requested by the gfx object.
<p>
Gfx objects are visible only on screen and will be ignored by most export
plugins. The main purpose of the gfx object is GUI enhancement - for example
breadboard support.
<p>
Gfx attributes intepreted by pcb-rnd:
<p>
<table border=1>
<caption><b>Gfx attributes</b>
<tr><th> gfx attribute name <th> description
<tr><td> render_level <td> if value is "under", render the gfx object before (under) other objects on the same layer, else after (above) other objects on the same layer
</table>
<p>
<h4> 2.4.9 Netlists </h4>
<p>
A netlist is a list of named logical networks. Each network is a list of
netlist terminals that should be connected. A netlist terminal is a pair
of subcircuit-refdes and pin-number (or pad-number). Thus a typical netlist
looks like the following:
<ul>
<li> net: GND
<ul>
<li> U1-2
<li> U2-7
<li> U3-7
<li> C1-1
</ul>
<li> net: Vcc
<ul>
<li> U1-3
<li> U2-14
<li> U3-14
<li> C1-2
</ul>
<li> net: strobe
<ul>
<li> U2-2
<li> U3-5
</ul>
</ul>
<p>
The netlist assumes subcircuit refdes are unique. If a subcircuit has multiple
instances of the same terminal number, the engine picks one randomly and
assumes there's an invisible, internal connection within the subcircuit.
<p>
Rat lines can be regenerated from the current netlist for missing connections.
Connections that are realized in copper but not present on the netlist, pcb-rnd
gives a "short circuit" warning. Both happens when the net is "optimized"
(upon user request).
<p>
The netlist is typically derived from a schematics by external tools
(such as gnetlist). The netlist can be imported (updated) any time. This
process is called "forward annotation".
<p>
It is also possible to make changes to the netlist from within pcb-rnd:
terminals can be swapped, subcircuit footprint replaced using <i>back annotation
actions</i>. Such actions will keep a list of intended netlist and subcircuit
changes, called the netlist patch. Pcb-rnd will keep these changes even
if a new version of the netlist is imported. It is possible to export the
netlist patch that can be imported in the schematics editor to change the
schematics - this process is called "back annotation". A new forward
annotation from the schematics editor to pcb-rnd will then cancel
the netlist/subcircuit changes as the new netlist import netlist matches
the intended (changed) netlist.
<h3> 2.5. Non-objects </h3>
<p>
The following objects are commonly used in the industry, but have no
special implementation in pcb-rnd but are created by using the above
objects.
<h4> Vias </h4>
<p>
A via is an electrically connected hole that connects copper rings to multiple
layers. In pcb-rnd, a via is always implemented using a <a href="#padstack">
padstack.</a>
<h4> Holes </h4>
<p>
A hole is a special case of a <a href="#padstack"> padstack:</a> it has
an unplated hole and typically does not have copper pad shapes but should
have mask cutout shape.
<h4> Test points, test pads</h4>
<p>
A test point or test pad is a <a href="#padstack"> padstack</a> that has
copper shape only on one of the outer copper layer and a mask cutout shape
over that layer.
<h4> Fiducials </h4>
<p>
A fiducial mark is a special case of a <a href="#padstack"> padstack </a>
very similar to the test point/pad.
<h4> Targets/marks </h4>
A mark or target (e.g. for layer alignment) is usually realized as a
<a href="#subcircuit"> subcircuit </a> it has more complex graphics that
doesn't fit in a padstack.
<h4> Using subcircuit instead of raw padstack </h4>
<p>
Holes, test points/pads and fiducials are often realized within a
<a href="#subcircuit"> subcircuit </a>, especially if they have a refdes
and present on the schematics. However, the only way to implement a hole
is using a padstack, so the resulting subcircuit for holes and test pins
will always have at least one padstack.
<h3> 2.6. Comparison of Physical world and pcb-rnd world terminology </h3>
<p>
<table border=1>
<caption><b>Pcb-rnd Terminology</b>
<tr><th> Physical board <th> pcb-rnd <th> Description
<tr><td> Layer <td> Layer Group <td> enables the user to design complex physical constructions
<tr><td> Copper layer <td> Layer group of type copper <td>
<tr><td> Component/Top copper layer<td> Layer group of type copper, location top <td>
<tr><td> Solder/bottom copper layer<td> Layer group of type copper, location bottom <td>
<tr><td> Substrate, prepreg, core <td> Layer group marked as substrate, hosting no logical layers<td> pcb-rnd does not yet handle properties of physical substrate information
<tr><td> Contour of the board <td> Boundary layer <td> designed using standard pcb-rnd objects
<tr><td> Outline routing path <td> Boundary layer <td> designed using standard pcb-rnd objects
<tr><td> Polygon pour <td> Polygon <td> an object available for design in any layer group
<tr><td> Plane <td> Polygon <td> see above
<tr><td> Mask (solder mask) <td> Layer group with implicit and potential explicit content <td> design layers available: automatic, additive, subtractive
<tr><td> Silk <td> Layer group with implicit and potential explicit content <td> design layers available: automatic, additive, subtractive
<tr><td> Paste (paste stencil) <td> Layer group with implicit and potential explicit content <td> design layers available: automatic, additive, subtractive
<tr><td> <td> Rats <td> assistive layer automatically generated with netlist and copper layer group connection data
<tr><td> Via <td> Padstack <td> a vertical construction that features a plated hole and copper pads around the hole
<tr><td> Pin <td> Padstack <td> a special via that is going to host a pin of a through-hole component soldered on the board
<tr><td> Pad <td> Padstack <td> a copper feature that is going to host a lead of a surface mount component
<tr><td> Hole, mounting hole <td> Padstack <td> special case of vias, with no plating or copper pads
<tr><td> Fiducial mark, test pad <td> Padstack <td> special case of pad
<tr><td> Element, module, part (on board)<td> Subcircuit <td> a placed instance of a library footprint
<tr><td> Footprint, land pattern <td> Footprint <td> reusable patterns stored in the footprint library
</table>
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