File: DIL%2018%20300.fp

package info (click to toggle)
pcb 20140316-3.1
  • links: PTS, VCS
  • area: main
  • in suites: stretch
  • size: 22,212 kB
  • ctags: 16,012
  • sloc: ansic: 123,955; sh: 7,306; yacc: 5,087; pascal: 4,118; makefile: 1,565; perl: 552; lex: 438; awk: 157; lisp: 86; tcl: 63; xml: 20
file content (30 lines) | stat: -rw-r--r-- 868 bytes parent folder | download | duplicates (5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
# retain backwards compatibility to older versions of PKG_DIL 
# which did not have ,, args
Element(0x00 "generic" "" "DIL 18 300" 220 100 3 100 0x00)
(
	Pin(50 50 60 28 "1" 0x101)
	Pin(50 150 60 28 "2" 0x01)
	Pin(50 250 60 28 "3" 0x01)
	Pin(50 350 60 28 "4" 0x01)
	Pin(50 450 60 28 "5" 0x01)
	Pin(50 550 60 28 "6" 0x01)
	Pin(50 650 60 28 "7" 0x01)
	Pin(50 750 60 28 "8" 0x01)
	Pin(50 850 60 28 "9" 0x01)
	Pin(350 850 60 28 "10" 0x01)
	Pin(350 750 60 28 "11" 0x01)
	Pin(350 650 60 28 "12" 0x01)
	Pin(350 550 60 28 "13" 0x01)
	Pin(350 450 60 28 "14" 0x01)
	Pin(350 350 60 28 "15" 0x01)
	Pin(350 250 60 28 "16" 0x01)
	Pin(350 150 60 28 "17" 0x01)
	Pin(350 50 60 28 "18" 0x01)
	ElementLine(0 0 0 900 10)
	ElementLine(0 900 400 900 10)
	ElementLine(400 900 400 0 10)
	ElementLine(0 0 150 0 10)
	ElementLine(250 0 400 0 10)
	ElementArc(200 0 50 50 0 180 10)
	Mark(50 50)
)