1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
|
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:64:64-p8:32:32-p9:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "hsail64"
; This file is originally from libclc
; *************************************************************************
define i32 @__clc_atomic_add_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_add_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_and_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_and_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_cmpxchg_addr1(i32 addrspace(1)* nocapture %ptr, i32 %compare, i32 %value) nounwind alwaysinline {
entry:
%0 = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %compare, i32 %value seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 0
ret i32 %1
}
define i32 @__clc_atomic_cmpxchg_addr3(i32 addrspace(2)* nocapture %ptr, i32 %compare, i32 %value) nounwind alwaysinline {
entry:
%0 = cmpxchg volatile i32 addrspace(2)* %ptr, i32 %compare, i32 %value seq_cst seq_cst
%1 = extractvalue { i32, i1 } %0, 0
ret i32 %1
}
define i32 @__clc_atomic_max_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_max_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_min_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_min_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile min i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_or_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_or_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umax_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umax_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umin_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_umin_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umin i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_sub_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_sub_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_xchg_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_xchg_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xchg i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_xor_addr1(i32 addrspace(1)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %value seq_cst
ret i32 %0
}
define i32 @__clc_atomic_xor_addr3(i32 addrspace(2)* nocapture %ptr, i32 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xor i32 addrspace(2)* %ptr, i32 %value seq_cst
ret i32 %0
}
; *************************************************************************
define i64 @__clc_atom_add_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_add_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile add i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_and_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_and_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile and i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_cmpxchg_addr1(i64 addrspace(1)* nocapture %ptr, i64 %compare, i64 %value) nounwind alwaysinline {
entry:
%0 = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %compare, i64 %value seq_cst seq_cst
%1 = extractvalue { i64, i1 } %0, 0
ret i64 %1
}
define i64 @__clc_atom_cmpxchg_addr3(i64 addrspace(2)* nocapture %ptr, i64 %compare, i64 %value) nounwind alwaysinline {
entry:
%0 = cmpxchg volatile i64 addrspace(2)* %ptr, i64 %compare, i64 %value seq_cst seq_cst
%1 = extractvalue { i64, i1 } %0, 0
ret i64 %1
}
define i64 @__clc_atom_max_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_max_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile max i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_min_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile min i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_min_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile min i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_or_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_or_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile or i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_umax_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_umax_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umax i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_umin_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umin i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_umin_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile umin i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_sub_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_sub_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile sub i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_xchg_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xchg i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_xchg_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xchg i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_xor_addr1(i64 addrspace(1)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xor i64 addrspace(1)* %ptr, i64 %value seq_cst
ret i64 %0
}
define i64 @__clc_atom_xor_addr3(i64 addrspace(2)* nocapture %ptr, i64 %value) nounwind alwaysinline {
entry:
%0 = atomicrmw volatile xor i64 addrspace(2)* %ptr, i64 %value seq_cst
ret i64 %0
}
|
