1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
|
::FROM-WRITER;
design top
{
device
{
architecture sa5p00;
device LFE5U-25F;
package CABGA381;
performance "8";
}
comp SLICE_0
[,,,,A0,B0,D0,C0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,]
{
logical
{
cellmodel-name SLICE;
program "MODE:LOGIC "
"K0::H0=0 "
"F0:F ";
primitive K0 i3_4_lut;
}
site R6C10A;
}
comp SLICE_1
[,,,,A0,B0,D0,C0,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,]
{
logical
{
cellmodel-name SLICE;
program "MODE:LOGIC "
"K0::H0=0 "
"F0:F ";
primitive K0 i3_4_lut;
}
site R6C40A;
}
signal q_c
{
signal-pins
// drivers
(SLICE_1, Q0),
// loads
(SLICE_0, A0);
route
R6C10_H02W0701.R6C10_A0;
}
}
|
