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CWD=$(shell pwd)
export COCOTB_REDUCED_LOG_FMT = 1
SIM ?= icarus
TOPLEVEL_LANG ?= verilog
ifeq ($(TOPLEVEL_LANG),verilog)
VERILOG_SOURCES =$(CWD)/hdl/verilog/tinyalu.sv
else ifeq ($(TOPLEVEL_LANG),vhdl)
VHDL_SOURCES=$(CWD)/hdl/vhdl/single_cycle_add_and_xor.vhd \
$(CWD)/hdl/vhdl/three_cycle_mult.vhd \
$(CWD)/hdl/vhdl/tinyalu.vhd
else
$(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
endif
ifeq ($(SIM), verilator)
# Enable processing of #delay statements
COMPILE_ARGS += --timing
endif
COCOTB_TEST_MODULES := testbench
TOPLEVEL = tinyalu
GHDL_ARGS := --ieee=synopsys
COCOTB_HDL_TIMEUNIT = 1us
COCOTB_HDL_TIMEPRECISION = 1us
include $(shell cocotb-config --makefiles)/Makefile.sim
include ../../checkclean.mk
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