File: mt7628-clk.h

package info (click to toggle)
qemu 1%3A10.0.6%2Bds-0%2Bdeb13u2
  • links: PTS, VCS
  • area: main
  • in suites: sid, trixie
  • size: 413,604 kB
  • sloc: ansic: 4,733,865; pascal: 114,808; python: 105,532; asm: 68,406; sh: 52,876; makefile: 27,469; perl: 18,777; cpp: 11,436; xml: 3,404; objc: 2,877; yacc: 2,505; php: 1,299; tcl: 1,296; lex: 1,110; sql: 71; awk: 43; sed: 35; javascript: 7
file content (37 lines) | stat: -rw-r--r-- 781 bytes parent folder | download | duplicates (9) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
 
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2019 MediaTek Inc.
 *
 * Author:  Weijie Gao <weijie.gao@mediatek.com>
 */

#ifndef _DT_BINDINGS_MT7628_CLK_H_
#define _DT_BINDINGS_MT7628_CLK_H_

/* Base clocks */
#define CLK_SYS				34
#define CLK_CPU				33
#define CLK_XTAL			32

/* Peripheral clocks */
#define CLK_PWM				31
#define CLK_SDXC			30
#define CLK_CRYPTO			29
#define CLK_MIPS_CNT			28
#define CLK_PCIE			26
#define CLK_UPHY			25
#define CLK_ETH				23
#define CLK_UART2			20
#define CLK_UART1			19
#define CLK_SPI				18
#define CLK_I2S				17
#define CLK_I2C				16
#define CLK_GDMA			14
#define CLK_PIO				13
#define CLK_UART0			12
#define CLK_PCM				11
#define CLK_MC				10
#define CLK_INTC			9
#define CLK_TIMER			8

#endif /* _DT_BINDINGS_MT7628_CLK_H_ */