1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
|
#! /usr/bin/env python3
# Generate test-avx.h from x86.csv
import csv
import sys
from fnmatch import fnmatch
archs = [
"SSE", "SSE2", "SSE3", "SSSE3", "SSE4_1", "SSE4_2",
"AES", "AVX", "AVX2", "AES+AVX", "VAES+AVX",
"F16C", "FMA",
]
ignore = set(["FISTTP",
"LDMXCSR", "VLDMXCSR", "STMXCSR", "VSTMXCSR"])
imask = {
'vBLENDPD': 0xff,
'vBLENDPS': 0x0f,
'CMP[PS][SD]': 0x07,
'VCMP[PS][SD]': 0x1f,
'vCVTPS2PH': 0x7,
'vDPPD': 0x33,
'vDPPS': 0xff,
'vEXTRACTPS': 0x03,
'vINSERTPS': 0xff,
'MPSADBW': 0x7,
'VMPSADBW': 0x3f,
'vPALIGNR': 0x3f,
'vPBLENDW': 0xff,
'vPCMP[EI]STR*': 0x0f,
'vPEXTRB': 0x0f,
'vPEXTRW': 0x07,
'vPEXTRD': 0x03,
'vPEXTRQ': 0x01,
'vPINSRB': 0x0f,
'vPINSRW': 0x07,
'vPINSRD': 0x03,
'vPINSRQ': 0x01,
'vPSHUF[DW]': 0xff,
'vPSHUF[LH]W': 0xff,
'vPS[LR][AL][WDQ]': 0x3f,
'vPS[RL]LDQ': 0x1f,
'vROUND[PS][SD]': 0x7,
'vSHUFPD': 0x0f,
'vSHUFPS': 0xff,
'vAESKEYGENASSIST': 0xff,
'VEXTRACT[FI]128': 0x01,
'VINSERT[FI]128': 0x01,
'VPBLENDD': 0xff,
'VPERM2[FI]128': 0xbb,
'VPERMPD': 0xff,
'VPERMQ': 0xff,
'VPERMILPS': 0xff,
'VPERMILPD': 0x0f,
}
def strip_comments(x):
for l in x:
if l != '' and l[0] != '#':
yield l
def reg_w(w):
if w == 8:
return 'al'
elif w == 16:
return 'ax'
elif w == 32:
return 'eax'
elif w == 64:
return 'rax'
raise Exception("bad reg_w %d" % w)
def mem_w(w):
if w == 8:
t = "BYTE"
elif w == 16:
t = "WORD"
elif w == 32:
t = "DWORD"
elif w == 64:
t = "QWORD"
elif w == 128:
t = "XMMWORD"
elif w == 256:
t = "YMMWORD"
else:
raise Exception()
return t + " PTR 32[rdx]"
class XMMArg():
isxmm = True
def __init__(self, reg, mw):
if mw not in [0, 8, 16, 32, 64, 128, 256]:
raise Exception("Bad /m width: %s" % w)
self.reg = reg
self.mw = mw
self.ismem = mw != 0
def regstr(self, n):
if n < 0:
return mem_w(self.mw)
else:
return "%smm%d" % (self.reg, n)
class MMArg():
isxmm = True
def __init__(self, mw):
if mw not in [0, 32, 64]:
raise Exception("Bad mem width: %s" % mw)
self.mw = mw
self.ismem = mw != 0
def regstr(self, n):
return "mm%d" % (n & 7)
def match(op, pattern):
if pattern[0] == 'v':
return fnmatch(op, pattern[1:]) or fnmatch(op, 'V'+pattern[1:])
return fnmatch(op, pattern)
class ArgVSIB():
isxmm = True
ismem = False
def __init__(self, reg, w):
if w not in [32, 64]:
raise Exception("Bad vsib width: %s" % w)
self.w = w
self.reg = reg
def regstr(self, n):
reg = "%smm%d" % (self.reg, n >> 2)
return "[rsi + %s * %d]" % (reg, 1 << (n & 3))
class ArgImm8u():
isxmm = False
ismem = False
def __init__(self, op):
for k, v in imask.items():
if match(op, k):
self.mask = imask[k];
return
raise Exception("Unknown immediate")
def vals(self):
mask = self.mask
yield 0
n = 0
while n != mask:
n += 1
while (n & ~mask) != 0:
n += (n & ~mask)
yield n
class ArgRM():
isxmm = False
def __init__(self, rw, mw):
if rw not in [8, 16, 32, 64]:
raise Exception("Bad r/w width: %s" % w)
if mw not in [0, 8, 16, 32, 64]:
raise Exception("Bad r/w width: %s" % w)
self.rw = rw
self.mw = mw
self.ismem = mw != 0
def regstr(self, n):
if n < 0:
return mem_w(self.mw)
else:
return reg_w(self.rw)
class ArgMem():
isxmm = False
ismem = True
def __init__(self, w):
if w not in [8, 16, 32, 64, 128, 256]:
raise Exception("Bad mem width: %s" % w)
self.w = w
def regstr(self, n):
return mem_w(self.w)
class SkipInstruction(Exception):
pass
def ArgGenerator(arg, op):
if arg[:3] == 'xmm' or arg[:3] == "ymm":
if "/" in arg:
r, m = arg.split('/')
if (m[0] != 'm'):
raise Exception("Expected /m: %s", arg)
return XMMArg(arg[0], int(m[1:]));
else:
return XMMArg(arg[0], 0);
elif arg[:2] == 'mm':
if "/" in arg:
r, m = arg.split('/')
if (m[0] != 'm'):
raise Exception("Expected /m: %s", arg)
return MMArg(int(m[1:]));
else:
return MMArg(0);
elif arg[:4] == 'imm8':
return ArgImm8u(op);
elif arg == '<XMM0>':
return None
elif arg[0] == 'r':
if '/m' in arg:
r, m = arg.split('/')
if (m[0] != 'm'):
raise Exception("Expected /m: %s", arg)
mw = int(m[1:])
if r == 'r':
rw = mw
else:
rw = int(r[1:])
return ArgRM(rw, mw)
return ArgRM(int(arg[1:]), 0);
elif arg[0] == 'm':
return ArgMem(int(arg[1:]))
elif arg[:2] == 'vm':
return ArgVSIB(arg[-1], int(arg[2:-1]))
else:
raise Exception("Unrecognised arg: %s", arg)
class InsnGenerator:
def __init__(self, op, args):
self.op = op
if op[-2:] in ["PH", "PS", "PD", "SS", "SD"]:
if op[-1] == 'H':
self.optype = 'F16'
elif op[-1] == 'S':
self.optype = 'F32'
else:
self.optype = 'F64'
else:
self.optype = 'I'
try:
self.args = list(ArgGenerator(a, op) for a in args)
if not any((x.isxmm for x in self.args)):
raise SkipInstruction
if len(self.args) > 0 and self.args[-1] is None:
self.args = self.args[:-1]
except SkipInstruction:
raise
except Exception as e:
raise Exception("Bad arg %s: %s" % (op, e))
def gen(self):
regs = (10, 11, 12)
dest = 9
nreg = len(self.args)
if nreg == 0:
yield self.op
return
if isinstance(self.args[-1], ArgImm8u):
nreg -= 1
immarg = self.args[-1]
else:
immarg = None
memarg = -1
for n, arg in enumerate(self.args):
if arg.ismem:
memarg = n
if (self.op.startswith("VGATHER") or self.op.startswith("VPGATHER")):
if "GATHERD" in self.op:
ireg = 13 << 2
else:
ireg = 14 << 2
regset = [
(dest, ireg | 0, regs[0]),
(dest, ireg | 1, regs[0]),
(dest, ireg | 2, regs[0]),
(dest, ireg | 3, regs[0]),
]
if memarg >= 0:
raise Exception("vsib with memory: %s" % self.op)
elif nreg == 1:
regset = [(regs[0],)]
if memarg == 0:
regset += [(-1,)]
elif nreg == 2:
regset = [
(regs[0], regs[1]),
(regs[0], regs[0]),
]
if memarg == 0:
regset += [(-1, regs[0])]
elif memarg == 1:
regset += [(dest, -1)]
elif nreg == 3:
regset = [
(dest, regs[0], regs[1]),
(dest, regs[0], regs[0]),
(regs[0], regs[0], regs[1]),
(regs[0], regs[1], regs[0]),
(regs[0], regs[0], regs[0]),
]
if memarg == 2:
regset += [
(dest, regs[0], -1),
(regs[0], regs[0], -1),
]
elif memarg > 0:
raise Exception("Memarg %d" % memarg)
elif nreg == 4:
regset = [
(dest, regs[0], regs[1], regs[2]),
(dest, regs[0], regs[0], regs[1]),
(dest, regs[0], regs[1], regs[0]),
(dest, regs[1], regs[0], regs[0]),
(dest, regs[0], regs[0], regs[0]),
(regs[0], regs[0], regs[1], regs[2]),
(regs[0], regs[1], regs[0], regs[2]),
(regs[0], regs[1], regs[2], regs[0]),
(regs[0], regs[0], regs[0], regs[1]),
(regs[0], regs[0], regs[1], regs[0]),
(regs[0], regs[1], regs[0], regs[0]),
(regs[0], regs[0], regs[0], regs[0]),
]
if memarg == 2:
regset += [
(dest, regs[0], -1, regs[1]),
(dest, regs[0], -1, regs[0]),
(regs[0], regs[0], -1, regs[1]),
(regs[0], regs[1], -1, regs[0]),
(regs[0], regs[0], -1, regs[0]),
]
elif memarg > 0:
raise Exception("Memarg4 %d" % memarg)
else:
raise Exception("Too many regs: %s(%d)" % (self.op, nreg))
for regv in regset:
argstr = []
for i in range(nreg):
arg = self.args[i]
argstr.append(arg.regstr(regv[i]))
if immarg is None:
yield self.op + ' ' + ','.join(argstr)
else:
for immval in immarg.vals():
yield self.op + ' ' + ','.join(argstr) + ',' + str(immval)
def split0(s):
if s == '':
return []
return s.split(',')
def main():
n = 0
if len(sys.argv) != 3:
print("Usage: test-avx.py x86.csv test-avx.h")
exit(1)
csvfile = open(sys.argv[1], 'r', newline='')
with open(sys.argv[2], "w") as outf:
outf.write("// Generated by test-avx.py. Do not edit.\n")
for row in csv.reader(strip_comments(csvfile)):
insn = row[0].replace(',', '').split()
if insn[0] in ignore:
continue
cpuid = row[6]
if cpuid in archs:
try:
g = InsnGenerator(insn[0], insn[1:])
for insn in g.gen():
outf.write('TEST(%d, "%s", %s)\n' % (n, insn, g.optype))
n += 1
except SkipInstruction:
pass
outf.write("#undef TEST\n")
csvfile.close()
if __name__ == "__main__":
main()
|
